Carry Skip 4Bit Blocks in Pass and DCVSL Logic

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Carry Skip 4-Bit Blocks in Pass and DCVSL Logic

• Michael Morgan
• Department of Electrical and Computer Engineering
• Microsystems Prototyping Laboratory
• Mississippi State University

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Carry Skip

• Poor Mans Acceleration Method
• Pass transistor implementation adds 25
  transistors
• DCVSL implementation adds 40 transistors
• Try to speed up worst case propagate
• 0 1 happens with 50 probability
• The average length of the carry chain in a k-bit
  addition is log2(1.25k)1

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Carry Skip Block Diagram
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Pass Transistors Overview

• Advantages
• Low power
• Good for Mux logic
• Easily sized
• Sizes decrease down a path
• Disadvantages
• No drive strength
• Signals degrade due to channel resistancemust
  buffer
• PMOS cannot pull down to Gnd
• NMOS cannot pull up to Vdd
• Good for Mux logic only

Control
Out
In
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DCVSL Overview

• Differential Cascade Voltage Switch Logic 2

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DCVSL Overview (continued)

• Advantages
• 2 PMOS per logic gate
• Dual rail
• Disadvantages
• Dual rail
• Sizing incorrect sizing will cause functional
  failures
• Power dissipated through crowbar current

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Pass/DCVSL Raw Data
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Results

• DCVSL is faster
• 200 for Tplh
• 25 for Tphl
• Why? Pass transistors have no drive
• Pass transistors consume 29 less power
• Why? No drive
• Also, DCVSL has crowbar current

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Conclusions

• Stick to CMOS!
• Pass transistors may seem novel, but must buffer
• I used full buffers
• DCVSL must be sized correctly, or gates will not
  even function!
• Also crowbar current can be power-hungry and slow

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References

• 1 Dr. J. C. Harden Basic Addition, Slide 14,
  http//www.ece.msstate.edu/classes/ece8053/present
  ations/08f02-basadd.ppt.
• 2 Dr. B. Reese DCVSL, Slide 1,
  http//www.ece.msstate.edu/reese/EE8273/lectures/
  dcvsl/dcvsl_files/frame.htm.