AMS2 JCrate TopLevel DAQ Computer Status at CSIST

1
AMS-2 J-Crate (Top-Level DAQ Computer) Status
at CSIST

• Wei-Ping, Yang -CSIST
• Dec. 1Dec. 5, 2003

2
J-crate From QM to QM2
3
J-Crate Current Status

• JSBC
• New heat sink for PPC750 and Regulator
• Measurement and prediction result mismatch for
  regulator
• JBU
• New firmware with Master/target CorePCI)
• JBP
• JBP V3 has failed (25 factory will give a report)

4
JSBC Thermal Analysis Result
5
J-crate Power Consumption
6
JSBC Heat Sink

• Extend heat sink and
• Mount Regulator here

7
New JSBC Heat Sink
8
CPC700 Package Dimension
9
PPC750 Package
10

• The gap between PPC750 and heat sink is 0.35mm ,
  0.4mm for CPC700
• For PPC700, height is from 2.65mm to 3.2mm (1.85
  to 2.2 after soldering)
• For CPC700, height is from 3.05mm to 2.5mm(1.6 to
  2.15 after soldering)
• If the gap is allowable, then we need to decide
  which kind of filler to be used between the
  PPC750 and heat sink
• For regulator, the metal part in the back side
  in DC output, so it need a insulator between the
  regulator and heat sink

11
New JBU Firmware
12
JBU PCI Controller Design

• Implement a Back-end DMA Control logic module
• For CorePCI I.P., replace Target/DMA function
  with Master/Target function
• Add three new DMA control register in
  Control/status Register (base address register
  1) area
• PCI address register (0x40)
• RAM address register (0x44)
• DMA control register (0x48)
• DMA transfer mechanism
• CPU set the DMA control register (BAR1)
• Back-end DMA Controller separate the transfer
  length into into 64 DWORDS and write to DMA
  registers
• Start one DMA transfer
• Repeat till data transferred completely

13
JBU Status

• Add CorePCI Master/target function into design
  file
• Definition new control/status register ( PCI
  address register,RAM address register,DMA control
  register)
• Modify back-end DMA controller according to
  simulation result
• Provide a new version JBU before end of Dec.
• Update design document before new version JBU
  delivered

14
Summary

• Circuit and PCB design are frozen
• The testing result of QM and QM2 seems good
• We are waiting for the start on signal for FM
  implementation