HighLevel Simulation of Substrate Noise Generation Including Power Supply Noise Coupling

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High-Level Simulation of Substrate Noise
Generation Including Power Supply Noise Coupling

• Marc van Heijningen

IMEC vzw, Leuven, Belgium
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Outline

• Motivation
• Methodology overview
• 1 - Library characterization
• 2 - Substrate noise simulation
• Simulation details
• Conclusions

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Substrate noise coupling is a problem in
mixed-signal ICs
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Two sources of substrate noiseswitching nodes
and power supply
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Existing approaches use low-level SPICE substrate
models

• accurate SPICE substrate models can be derived
  from a layout using existing CAD tools
• SPICE simulation of the entire circuit is
  necessary
• not feasible for large digital circuits
• ? Simulation at higher level required

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Our goal high-level substrate noise coupling
analysis

• Simulate the substrate noise generation of large
  digital circuits at VHDL gate level
• Include both noise coupling from switching gates
  and power supply noise coupling
• Include external (package, PCB) parasitics
• ? combine this digital substrate noise simulation
  with the simulation of the analog part, which
  includes a detailed substrate model
• analyze performance degradation
• make the analog circuit less sensitive
• make the digital circuit less noisy

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Methodology overview (1)Library characterization
digital standard cell library
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Basis for library characterization

• Extraction of substrate noise generation is
  performed for each gate individually
• Noise generation is defined by
• input switching activity
• state of the other inputs
• in case of flip-flops, also previous output state
• Noise generation current injection into the
  substrate
• Specific for epi-type substrates
• substrate one electrical node

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SPICE substrate model used for extracting the
noise injection
in
Vss
Vdd
out
p
n
n
p
p
n
n-well
p-well
p- epi
p bulk
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Substrate model is approximated by a parallel
resistor and capacitor
Vss
Vdd
Rsub
Cwell
substrate
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Model approximation is valid up to several GHz
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Full SPICE model is reduced to a substrate noise
macro model
Vss
Vdd
Rsub
Cwell
Vsubstrate
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Macro model example inverter
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Macro model example flip-flop
Q
D
QN
CP
CD
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Methodology overview (1)Library characterization
digital standard cell library
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VHDL library extension to record input switching
activity
A
VHDL gate model
Z
B
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Methodology overview (2)Substrate noise
simulation
substrate noise macro model library
event based model library
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Switching event extraction from a standard
gate-level VHDL simulation
55 NS 1H00------ FD2Q buf_reg_3 55 NS
1H01------ FD2 buf_reg_0 55.924 NS 11H1------ FD2
buf_reg_0 57.063 NS L1-------- EO U31 57.063 NS
L1-------- ND2 U29 57.08 NS 0H-------- EN
U30 57.08 NS H--------- IV U26 57.268 NS
0L-------- EO U31 57.268 NS 0L-------- ND2
U29 57.279 NS L0-------- NR2 U25 57.492 NS
H1-------- EN U30 57.492 NS 0H-------- NR2 U25 60
NS 1L00------ FD2Q buf_reg_1 60 NS 1L11------
FD2Q buf_reg_2 60 NS 1L00------ FD2Q
buf_reg_3 60 NS 1L10------ FD2 buf_reg_0 65 NS
1H00------ FD2Q buf_reg_1 65 NS 1H11------
FD2Q buf_reg_2 65 NS 1H00------ FD2Q
buf_reg_3 65 NS 1H10------ FD2 buf_reg_0 65.924
NS 11L0------ FD2 buf_reg_0
VHDL gate-level simulation with switching
event extraction
calculate total noise currents
time activity cell-type instance
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Total substrate noise simulation model (for
epi-type substrates)
Vss
Vdd
Vsubstrate
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More accurate simulation models required for
non-epi substrates
Vdd
Vdd
Vss
Vss
Substrate 3D resistive mesh network
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Simulation of substrate noise with and without
(wirebond) inductance
4-bit counter 32 gates 13 switching events
after rising clock edge (55ns) also noise from
falling clock edge (60ns)
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Also on-chip power supply noise is simulated
4-bit counter 32 gates
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Accurate high-level simulation of substrate noise
and supply current
2 8-bit counters and a 16-bit multiplier 1000
gates 170 switching events after rising clock
edge (60ns)
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Simulation times and details
counter multiplier Robo4 gates 34
1k 80k f.clkMHz 100 42 160 cycles
50 208 800 SPICE 435 sec 37 hours
--- High-level 6.2 sec 5.5 min. 42
min. speed-up 70 x 404 x ---
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Conclusions

• High-level modeling and simulation of substrate
  noise generation by large digital circuits
• for noise coupling from switching transistors
• for power supply noise coupling
• with package (and PCB) parasitics
• Simulate the substrate noise (as current
  impedance)
• Simulate power supply noise and current
  consumption
• Good agreement with full SPICE level simulations
• Large speed-up with respect to a SPICE simulation

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Ongoing / future work

• Improve glitch handling
• Include load dependency of current waveforms
• Include rise/fall time dependency
• Include multiple power domains
• Extend the methodology to high-ohmic substrates