Simulated Evolution Algorithm for Multi-Objective VLSI Netlist Bi-Partitioning

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Simulated Evolution Algorithm for Multi-Objective
VLSI Netlist Bi-Partitioning

• Sadiq M. Sait, Aiman El-Maleh, Raslan Al-Abaji
• King Fahd University of Petroleum Minerals
• Dhahran, Saudi Arabia
• 27th May, ISCAS-2003, Bangkok, Thailand

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Outline

• Introduction
• Problem Formulation
• Cost Functions
• Proposed Approach
• Experimental Results
• Conclusion

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VLSI Technology Trends
The challenges to sustain such a fast growth to
achieve giga-scale integration have shifted in a
large degree, from the process of manufacturing
technologies to the design technology. New issues
have also come up.
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VLSI Design Cycle
VLSI design process comprises a number of levels

1. System Specification
2. Functional Design
3. Logic Design
4. Circuit Design
5. Physical Design
6. Design Verification
7. Fabrication
8. Packaging Testing and Debugging

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Physical Design
What is Physical Design? A process that
translates a structural (netlist) description
into a geometric description that is used to
manufacture a chip.

• The physical design cycle consists of
• Partitioning
• Floorplanning and Placement
• Routing
• Compaction
• Why do we need Partitioning ?

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Levels of Partitioning
System
System Level Partitioning
PCBs
Board Level Partitioning
Chips
Chip Level Partitioning
Subcircuits /Blocks
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Classification of Partitioning Algorithms
Partitioning Algorithms
Group Migration
Iterative Heuristics
Performance Driven
Others

1. Lawler et al.
2. Vaishnav
3. Choi et al.
4. Junichiro et al.

1. Spectral
2. Multilevel Spectral

1. Kernighan-Lin
2. Fiduccia-Mattheyeses (FM)
3. Multilevel K-way Partitioning

1. Simulated Annealing
2. Simulated Evolution
3. Tabu Search
4. Genetic Algorithm

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Related previous Work
1969 A bottom-up approach for delay optimization (clustering) was proposed by Lawler et al.
1998 A circuit partitioning algorithm under path delay constraint is proposed by junichiro et al. The proposed algorithm consists of the clustering and iterative improvement phases.
1999 Two low power oriented techniques based on simulated annealing (SA) algorithm by choi et al.
1999 Enumerative partitioning algorithm targeting low power were proposed by Vaishnav et al. Enumerates alternate partitioning and selects a partitioning that has the same delay but less power dissipation.
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Motivation Objective

• Need for Power optimization
• Portable devices
• Power consumption is a hindrance to further
  integration
• Increasing clock frequency
• Need for Delay optimization
• In current sub micron design wire delays tend to
  dominate gate delay.
• Larger die size imply long on-chip wires which
  affect performance
• Delay due to off-chip capacitance
• Objectives Power, Delay Cutset are
  optimized
• Constraint Balanced partitions (with some
  tolerance)

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Problem formulation

• The circuit is modeled as a hypergraph H(V,E),
  where Vv1,v2,v3, vn is a set of modules
  (cells)
• And Ee1, e2, e3, ek is a set of hyperedges.
  Being the set of signal nets, each net is a
  subset of V containing the modules that the net
  connects.
• A 2-way partitioning of a set of nodes V is to
  determine subsets VA and VB such that VA ?VB
  V and VA ?VB ?

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Cutset

• Based on hypergraph model H (V, E)
• Cost c(e) 1 if e spans more than 1 block
• Cutset sum of hyperedge costs
• Efficient gain computation and update

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Delay

• path ? SE1 ? C1?C4?C5?SE2.
• Delay ? CDSE1 CDC1 CDC4 CDC5 CDSE2
• CDC1 BDC1 LFC1 ( Coffchip CINPC2 CINPC3
  CINPC4)

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Power
The average dynamic power consumed by CMOS logic
gate in a synchronous circuit is given by
Ni is the number of output gate transition per
cycle (Switching Probability)
load capacitance Load Capacitances before
Partitioning load due to off chip capacitance
Total Power dissipation of a Circuit
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Unifying Objectives by Fuzzy logic
Weighted Sum Approach

1. Problems in choosing weights
2. Need to tune for every circuit

• Imprecise values of the objectives
• Best represented by linguistic terms that are
  basis of fuzzy algebra
• Conflicting objectives
• Operators for aggregating function

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Fuzzy logic for Multi-objective function

• The cost to membership mapping
• Linguistic fuzzy rule for combining the
  membership values in an aggregating function
• Translation of the linguistic rule in form of
  appropriate fuzzy operators
• Fuzzy operators
• And-like operators Min operator ? min (?1,
  ?2)
• And-like OWA ?? min (?1,?2) ½ (1-?) (?1
  ?2)
• Or-like operators Max operator ? max (?1, ?2)
• Or-like OWA ?? max (?1,?2) ½ (1-?) (?1
  ?2)
• Where ? is a constant in range 0,1

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Membership functions

• Where Oi and Ci are lower bound and actual cost
  of objective i
• i(x) is the membership of solution x in set good
  i gi is the relative acceptance limit for
  each objective.

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Fuzzy linguistic rule Cost function
A good partitioning can be described by the
following fuzzy rule IF solution has small
cutset AND low power AND short delay AND good
Balance THEN it is a good solution The above
rule is translated to AND-like OWA
Represent the total Fuzzy fitness of the
solution, our aim is to Maximize this fitness
Respectively (Cutset, Power, Delay, Balance)
Fitness
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Simulated Evolution
Algorithm Simulated_Evolution Begin  Start with
an initial feasible Partition S
Repeat Evaluation Evaluate Gi (goodness)
for all modules Selection
For each Vi (cell) DO
begin if Random Rm gt Gi then
select the cell End
For Allocation For each selected Vi (cell) DO
begin Move
the cell to destination block.
End For Until Stopping criteria is
satisfied. Return best solution. End
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Cut goodness
di set of all nets, connected and not cut. wi
set of all nets, connected and cut.
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Power Goodness
Vi is the set of all nets connected and Ui is the
set of all nets connected and cut.
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Delay Goodness
Ki is the set of cells in all paths passing by
cell i. Li is the set of cells in all paths
passing by cell i and are not in same block as i.
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Final selection Fuzzy rule
IF cell i is near its optimal cut-set goodness
as compared to other cells   AND
AND THEN it has a high goodness.
near its optimal power goodness compared to
other cells
near its optimal net delay goodness as compared
to other cells OR T(max)(i) is much
smaller than Tmax
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Experimental Results
ISCAS 85-89 Benchmark Circuits
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SimE versus Tabu Search GA against time
Circuit s13207
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SimE results were better than TS and GA, with
faster execution time.
Experimental Results SimE versus TS and GA
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Conclusion

• The present work addressed the issue of
  partitioning VLSI circuits with the objective of
  reducing power and delay (in addition to nets
  cut)
• Fuzzy logic was resorted to for combining
  multi-objectives
• Iterative algorithms (GA, SA, and SimE) were
  investigated and compared for performance in
  terms of quality of solution and run time
• SimE outperformed TS and GA in terms of quality
  of solution and execution time

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Thank you
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Fuzzy Goodness
Tmax delay of most critical path in current
iteration. T(max)(i) delay of longest path
traversing cell i. Xpath Tmax / T(max)(i)
Respectively (Cutset, Power, Delay ) goodness.