Bob%20Hirosky

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L2beta Introduction
L2betas a stable source of processing power for
DØ Level2 Goals Commercial (replaceable)
components Provide replacement/upgrade
path Match requirements for L2Alphas Minimize
impact to experiments manpower hardware
development online software commissioning
effort Fastest possible development
time (timescale of RunIIa)
http//galileo.phys.virginia.edu/rjh2j/l2beta
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Design Approach
Break off CPU functions into commercial
SBC Implement custom I/O to as large an extent
as possible in Firmware Use factory-made PCI
interface, to lighten firmware complexity
9U board
6U board
mezzanine board
Hard drive
FPGA
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Functional Requirements

• Our aim is to develop a system that is both a
  functional match for the L2Alphas and supports
  both hardware and software compatibility
• to minimize impact on the trigger commissioning
  efforts.
• Functional requirements can be broken down into
  these categories
• Processing power
• OS/Software tools
• VME Support
• Custom I/O (TSI, MBus)
• Mechanical and Electrical

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CPU Requirements
Processing power 500 MHz 21164 2 integer, 2
floating pipes 64 bits wide (used in bit
searches and PIO) 96kB on-chip L2 cache 3-way
associative enough cache for data for event
enough instructions for 24 µsec of non-looping
execution (L3 cache (4MB) does not work, doesnt
SEEM to be needed because of characteristics of
L2 cache above) SI95 15 SF95 21 Executes L2
algorithms lt 50µsec/event
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Performance Benchmarks for common CPUs
CPU Specint95 Specfp95
Alpha 500 MHz 15 21
PIII 800 MHz 38 29
PIII 850 MHz 41 35
PIII 933 MHz 45 39
PIII 1000MHz 48 41
Integer performance is key for most L2
processing Tests include running of
compilers/interpreters, compression algorithms,
data base, chip simulations
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Modern CPUs performs well in comparison PIII on
chip Cache 256K vs 96K in Alpha, room for appx.
3 times the instructions with an event in
memory. Faster memory access w/ modern
RAMcontrollers PIII SBCs readily available
CPU section debugging is a warranty issue!
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SBC of Choice VMIC 7740(50) PIII 850
MHZ 100MHz x 64 bits RAM Bus Integrated UII
(VME support built in!) Single Slot
Design PMC expansion site
Single Vendor? NO! (Concurrent Tech SBS/Bit3)
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Advantages of PIII based CPU Popular
commercial products support Ongoing product
development Mature LINUX/OS support Commercial,
well supported, software readily available
KAI C Match to Alpha byte ordering Closeness to
Alpha Linux code Software development minimized
(short list to SW compatibility) - rewrite
device drivers - install memory access module
(Alpha version was developed from Intel Linux)
maybe, but maybe not necessary - interrupt
handling requires some thought, but Alpha
experience should provide a big jumpstart
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Custom I/O Functions
Strongest functional requirement is DMA 80-100
MB/s Data rate from MBus (FIFOs) to CPU Memory
required Also short latency times for MBus
programmed I/O even during DMA transfers
Ability to generate PCI interrupts Provide
register sets/functions compatible with L2Alphas
Custom I/O to be implemented in Xilinx XCV405E
FPGA (More details in PCI interface/Firmware
talks)
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DMA performance is mainly limited by PCI
interface The VME-based PIII cards all use PCI
33MHz x 32-bits Max Bandwidth 132MB/s This
rate is explicitly supported by memory controller
chips, thus efficient management of MBus Data to
PCI feed is the key. We propose using a hardware
PCI interface (PLX 9054) considering quanta of
DØ data sources and latency times for start of
DMA gt 100MB/s achievable gt80MB/s w/ periodic
DMA interruptions by PIO
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Electrical
L2 Alphas power requirements 172 W Estimates
for L2beta 58W Saving 104W Or (at 0.10/kWh)
3000/year for 30 boards
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Collaboration
Organization Device Drivers/Development Env.
UVa 9U Mezzanine Card Engineering
Orsay Firmware Maryland Orsay
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Present Status
1st 7740 to arrive w/ the week for start of
software development Block diagrams for
Electrical Firmware Mechanical prototype work
underway Ready to start detailed schematics
deliver prototypes by end of summer