Network on Chip Architecture Project Summary and Key Achievements

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Network on Chip ArchitectureProject Summary and
Key Achievements

• Kari Tiensyrjä
• VTT Electronics
• Oulu, Finland

NOCARC project
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Outline

• Research Objectives
• Research Organisation
• Key Achievements
• Publications, Dissemination and Co-operation
• Future Plans
• Conclusions

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Research Objectives

• In 2008, a Network-on-Chip (NoC) can have billion
  transistors, and accommodate tens of computer
  like resources (1 NoC gt 200 SoCs, 1 NOC capacity
  ? 100-10000 GIPS, )
• Research hypothesis is that current architectures
  and design approaches do not scale enough

• Objectives
• Novel architecture template called network on
  chip, i.e. NOC for future integrated
  telecommunication systems
• Design methodology that supports definition of
  application specific architecture, configuration
  of architecture and co-optimisation of both
  architecture and applications

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Research Organisation

• Workpackages
• WP1 NoC Concept
• WP2 NoC Architecture
• WP3 Decision Support
• WP4 Quality Estimation
• WP5 Design Tools
• Figures
• 2001 -2003
• 1000000
• 10 person years
• Further Information
• http//www.ele.kth.se/NOC/

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Key Achievements

• Milestone NoC Concept paper has been achieved,
  and published in ISVLSI2002
• NoC architecture principles topology, network,
  resources, communication, regions
• Design methodology backbone, platform, system
• NoC architecture studies have been published in
  IEEE Micro, JSA, WSEAS2002, SSGRR2002w,
  NorChip2002 and submitted to DATE2003
• Network communication for NoC simulator,
  protocol stack, switch
• Parallel computer for NoC multi-threaded
  processor, memory structures, switch, functional
  simulator
• Physical feasibility issues wire-ability,
  timing, power distribution
• NoC decision support and quality estimation
  studies have been published in DATE2002,
  CODES2002, DSD2002, NorChip2002 and accepted to
  VLSI2003

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Publications, Dissemination and Co-operation

• 21 papers
• 3 journal papers published, 1 accepted, 1 (with
  COMPLAIN) submitted
• 12 conference papers published, 1 accepted, 3
  submitted
• 1 magazine paper
• Theses, tutorials, training, reports
• 3 MSc theses
• ESSCIRC2001 tutorial (with COMPLAIN)
• KTH SoC master programme lectures (with COMPLAIN)
• 2 technical reports
• NoC Book (with COMPLAIN and external experts)
  to appear 2003
• Contribution to 6 chapters (out of 15)
• 3 steering group, 5 technical, 2 working
  meetings, researcher visits

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Future Plans

• Research work continues in WP2-5 according to
  research plan

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Conclusions

• 1 billion transistor NoCs are expected to be used
  in products by 2008
• Network communication, tens or even hundreds of
  computer-like resources in heterogenous case,
  homogeneous parallel computers
• Complexity of a NoC equals to that of a board in
  current basestation
• Development of such a NoC system will be a huge
  effort
• Reuse has to be enhanced through regular
  structures and layered design methodology
• Backbone, platform, system based design
  methodology approach provides variability,
  performance and cost-efficiency
• Each layer of the design methodology should
  follow a pattern Analysis - Decision -
  Estimation - Validation
• Related methods are the cornerstones of NOC
  development
• Tool support for decision making, quality
  estimation and validation