RADAR: RETAware Detailed Routing Using Fast Lithography Simulations

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RADAR RET-Aware Detailed Routing Using Fast
Lithography Simulations

• Joydeep Mitra, Peng Yu, David Z. Pan
• ECE Department
• Univ. of Texas at Austin

Partially sponsored by IBM, Intel and Software
from KLA-Tencor, Sigma-C
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Outline

• Motivation
• Fast Lithography Simulation
• Edge Placement Error Map
• EPE map based detailed routing
• Results
• Conclusion

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Motivation

• OPC features lead to mask data volume explosion.
• Increase in mask synthesis and verification time.
• Increase in mask cost!!
• Partially solved by Litho-aware design rules.
• Leads to explosion of physical design rules.
• Clear need for true litho-aware physical design
  automation

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Our Contribution

• Raise lithography modeling up to design
  implementation level
• Model-based vs. rule-based
• EPE map as a manufacturing effort metric
• Fast lithography simulation to generate EPE map
• Aerial image as the first order approximation
• Basic principle pre-compute image density
  convolution table for fast table lookup
• Two routing techniques to reduce EPE hotspots
• Wire spreading
• Ripup-Reroute (RR) with blockages

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Edge Placement Error Map

• A concept similar to congestion or thermal
  hotspot map
• Measurement of RET effort
• Work seamlessly with existing CAD flow

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EPE-Map Based RADAR Flow
Initial design closure detailed routing
EPE map display
Wire spreading and ripup and reroute
Re-simulate EPE hot spots if needed
Full chip fast litho simulation.
Routing window and blockage creation
Accept new route
EPE below threshold?
Keep old route
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Fast Aerial Image Simulation

• Fast lithography simulation to generate EPE map
• Aerial image is the first order approximation
  (resist not considered)
• Basic principle
• Decomposition
• Pre-compute image density convolution table for
  fast table lookup

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Aerial Image Simulation

• For coherent light entering mask
• Intensity equation at image plane
• Linear system, hence convolution applies

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Simulation control point and Intensity support
region

• Support region 1-4µm in perimeter or a
• multiple of resolution?/NA

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Efficient Table Look-up

• EPE computation store convolution table for
  rectangles w.r.t the top-right reference point

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Threshold Model
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RADAR RET-Aware Detailed Routing

• Use EPE map to guide RADAR
• Do not need to run lithography simulations often
• Rip-up-and-reroute
• Focus on EPE hotspots
• Re-simulate EPE only if necessary (rerouted
  regions)
• Store EPE influencing neighbor list for router to
  avoid those neighbors with high EPE impacts
• Routing blockage generation and wire spreading
• Protect safe regions with low EPE

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EPE Map During Routing

• Generate EPE for each control point (points
  that may have large edge placement errors) in
  design
• Each EPE control point has a ranked list of
  neighboring wires that contribute to the EPE
• Limited control point generation, dense at
  corners, sparse at long edges.
• Abstract a normalized EPE density for an entire
  routing segment

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Intelligent Ripup Reroute
N1
Routing blockage
S1
N2
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Experimental Results on a 65nm Industry Design
After wire spreading 12 EPE reduction with
10 WL increase
Initial routing (after design closure)
After RR 40 EPE reduction 5 WL increase
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Experimental Results

• EPE reduced by 40
• wirelength increased 5

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Simulation speed

• 650K std cell block (many hundred macros)
• 3000u X 3000u
• Metal1 (90nm technology node)
• Checked 1024 regions
• 1673880 stripified geometries
• 50271712 control points
• 131.64 seconds on a linux box!

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Conclusions

• Raised Lithography modeling up to design
  implementation level.
• EPE map manufacturing effort metric.
• Two routing techniques to reduce EPE.
• Ripup Reroute using blockages showed promising
  results.