A Tool for SEU Analysis of HDL Datapaths

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A Tool for SEU Analysis of HDL Datapaths

• Kevin M. Irick

2
Motivation

• SE due to leading combination circuits will
  exceed those caused by direct particle strikes on
  memory elements
• Early analysis of Datapath robustness and
  identification of Critical SEU paths
• Industry initiative towards SE characterization
  in cell libraries

3
Motivation

• SE due to leading combination circuits will
  exceed those caused by direct particle strikes on
  memory elements

• Obvious
• Reduced feature sizes will result in smaller
  nodal capacitances, and hence reduced charge
  collection of the node.

Feature Scaling
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Motivation

• SE due to leading combination circuits will
  exceed those caused by direct particle strikes on
  memory elements

• Not So Obvious
• Current microarchitectural trend is to reduce the
  logic depth between pipeline stages, while
  increasing the number of stages overall.
  However, as the logic depth within stages
  decreases the probability of a glitch being
  attenuated before reaching a latch input
  decreases.
• In general increased pipeline stages lends to
  increased clock frequency. As clock frequency
  increases the latching window of pipeline stages
  increase and the probability of an SEU
  propagating to a latch input becoming an SE
  increases.

5
Motivation

• SE due to leading combination circuits will
  exceed those caused by direct particle strikes on
  memory elements

Microarchitecture Advances
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Motivation

• Early analysis of Datapath robustness and
  identification of Critical SEU paths

• Datapath Design Goals
• Ideally the designer should analyze the datapath
  on a path-by-path basis due to the inverse
  relation of performance and robustness (speed vs.
  robustness).
• Ideally the designer should analyze the relative
  robustness of combination paths early in the
  design flow as close to HDL description coding
  as possible.
• Ideally the designer should not have to perform
  extensive simulations to characterize the SE
  susceptibilty of a logic path (coverage problem).

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Motivation

• Industry initiative towards SE characterization
  in cell libraries

• Industry Initiative
• Standard cell providers should be concious of the
  impact of soft errors in their standard cell
  libraries. In addition to detailed timing and
  power information, providers should provide SE
  profiling data for each cell in the library.
• Moreover, the task of modeling the SE rates and
  upset pulse width as a function of injection
  charge is the duty of any quality standard cell
  provider. This is primarily due to the fact that
  the spice information for a cell is not normally
  available to the end-user.

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Motivation

• But Why Paths?

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Proposed Approach

• Use probabilistic models of gate susceptibility,
  pulse duration, and clock arrival time.

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Proposed Approach

• Definitions
• PUpsetPath(vi, vi-1,. . . vi-n) is the
  probability that an SE propagating through the
  path specified by (vi, vi-1, . . . vi-n) is
  captured by the terminating latch.
• PErrorOriginate(vi) is the probability than an
  SE will originate at node vi. This probability
  is a strong function of cell attributes that vary
  depending on parameters including/but not limited
  to temperature, input state, load capacitance,
  cell area, and transistor sizing. The
  PErrorOriginate(vi) metric should be provided as
  a cell parameter from the library provider.
• PPulseExceed is the probability that for a given
  range of particle charge amplitude that may
  strike a cell, the resulting error pulse width on
  the output of the victim cell exceeds the total
  inertial reject width of the succeeding cells on
  the path leading to the latch. 2 Shows that a
  relatively accurate estimation of pulse width can
  be determined by equation 1. Since PW is linear
  in I0 it is sufficient to find the minimum
  current that results in a PW that exceeds the
  total inertial reject rating of the succeeding
  path and define PPulseExceed as the percentage of
  the charge amplitude range exceeding the
  threshold value over the entire charge amplitude
  range.

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Proposed Approach

• Definitions (continued)
• PLogicMasked is the probability that an upset
  occurring at the primary input of a cell is not
  propagated to the output because the current
  output of the gate is a function only of the
  other primary inputs. The critical input states
  for which an input error will propagate to the
  output can be determined for each cell function.
  PLogicMasked is thus the probability that the
  gate is not in one of the predetermined critical
  states.
• PLatchWindow is the probability than an SE that
  propagates to the end of a path arrives at the
  terminating latch within the clock time frame
  that causes the upset to be latched.
  PLatchWindow is simply the percentage of latch
  window (consisting of setup and hold times) to
  total clock period.

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Implementation

• Specify cell specific characteristics as Verilog
  specparam constants
• Use existing language constructs to pass
  information to the simulator (No ad-hoc parameter
  passing or auxiliary file parsing).
• Allows default values to be used for non-existent
  parameters.
• Use Verilog Programming Interface, VPI, to
  implement path characterization routine
• Promotes simulator non-dependency. The VPI
  functions only have to be recompiled and linked
  to the specific simulator.
• C/C Code is easily modified to incorporate
  better probabilistic models.

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Implementation

• Specify cell specific characteristics as Verilog
  specparam constants
• Example Well structured and informative cell
  description of 2-Input AND gate

module AN2 (o,a,b) // 2-input AND gate standard
cell output o input a, b and
(o,a,b) specify specparam InputLoada
0.2 specparam InputLoadb 0.3 //input-s
tate specific SEU probability specparam
ProbabilityUpset_00 0.05 specparam
ProbabilityUpset_01 0.35 . . . specpara
m ProbabilityUpset_11 0.15 endspecify endmodu
le
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Implementation

• Use Verilog Programming Interface, VPI, to
  implement path characterization routine
• Algorithm

TotalInertialRejectSucc0 For (jCell(x).Succesor
jPath.Member j!TerminatingLatch j)
TotalInertialRejectSuccCell(j).InertialRejec
tWidth For (iCell(x).charge_range_min
iltCell(x).charge_range_max icharge_resolution)
if (Cell(x).PulseWidth(i)gtTotalInertialRejectS
ucc)then break PPulseExceed
(Cell(x).charge_range_max i)/(Cell(x).charge_ran
ge_max Cell(x).charge_range_min)
PErrorOriginate (Cell(x).probability_upset PLog
icMasked 1 For (jCell(x).Succesor
jPath.Member j!TerminatingLatch j)
PLogicMaskedCell(j).probability_in_critical_
state/(2Cell(j).NumInputs) PLatchWindow
TerminatingLatch.Window/Clock.Frequency PUpsetPat
h PPulseExceed PErrorOriginate
(1-PLogicMasked) PLatchWindow
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Future Work

• How do we characterize reconvergent paths?
• Default SE Rate estimates if not provided?
• SE Driven logic Restructuring?
• Better pulse-stretching models!
• Identify dominate cells!
• Integrate with Place and Route!!!

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References

• 1Johnston, A. 2000. Scaling and technology
  issues for soft error rates. In Proceedings of
  4th Annual Research Conference on Reliability.
  Stanford University, Stanford, Calif.
• 2H. Cha and J. H. Patel, A logic-level model
  for a-particle hits in CMOS circuits, in
  Proceedings of the International Conference on
  Computer Design, pp. 538542, Oct. 1993.
• 3H. Cha, E. M. Rudnick, J. H. Patel, R. K.
  Iyer, and G. S. Choi, A gate-level simulation
  environment for alpha-particle-induced transient
  faults," IEEE Trans. on Computers, vol. 45, pp.
  12481256, Nov. 1996.
• 4J. K. Hass, Probabilistic estimates of upset
  caused by single event transients," 8th NASA
  Symposium on VLSI Design, 1999.
• 5K. N. Patel, I. L. Makov, and J. P. Hayes,
  Evaluating Circuit Reliability Under
  Probabilistic Gate-Level Fault Models, IWLS,
  Laguna Beach, CA, May 2003.