EKV Compact Model

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EKV Compact Model Extension for High-Voltage
Lateral DMOS Transistors
N. Hefyene (1) C. Anghel (1) J.M. Sallese
(1) A.M. Ionescu (1)
(1) EPFL, Lausanne, Switzerland Contact
naser.hefyene_at_epfl.ch
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Outline
Investigated HV devices Intrinsic-Drain
voltage concept MESDRIFT structure Drift
resistance modeling EKV Model extension to HV
DMOS transistors Model Parameter Model
vs. Measurements Optimizing Strategy
Advantages Limitations Future Developements
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• INVETIGATED STRUCTURES

EXtended lateral DMOS architecture (XDMOS)
0.7 ?m HV-CMOS technology from Alcatel
Microelectronics (AMIS)
K-point (VK)

• n-channel transistor
• Lch 4mm
• ? not self-aligned

Intrinsic channel
Drift region
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• INTRINSIC - DRAIN
• VOLTAGE CONCEPT

• Intrinsic DMOS channel behaves like
• a low-voltage MOSFET
• à model the intrinsic DMOS
• channel with a standard
• low-voltage MOSFET model
• (like BSIM or EKV)
• separately model the characteristics
• of the drift region

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• MESDRIFT a new test structure

MESDRIFT structure à n-implant near the
channel - drift region delimitation à
high-impedance voltmeter to monitor the VK
potential

• Features
• small dimensions of the K-contact compared
• to the global device width (10 ? 200 ?m)
• à minor influences on the global device
  characteristics are expected

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• XDMOS vs. MESDRIFT
• DC characteristics (W 40 ?m)

• increased leakage currents in the sub-threshold
  region

• slight shift in VDBR for the MESDRIFT test
  structure at low VG (lt5)

• overall good match between XDMOS and MESDRIFT
  characteristics

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• MESDRIFT typical extracted
• Drift characteristics

• VK potential evolution with external biases ? as
  predicted by 2D numerical simulation
• VKä VDä
• VKæ VGä

• Drift resistance evolution with external biases
  RD (VD VK) ? ID
• in agreement with 2D numerical simulations
  (better at high VG , due to the formation of a
  drift accumulation layer beneath gate oxide)

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• DRIFT RESISTANCE MODELING

The proposed quasi-empirical drift expression

• rD0, rD1, ? 0, ?1, ?0, ?2, ?1 ?0 ? room
  temperature parameters (T0)
• m and n ? temperature dependence parameters (T)

Features ? limited number of
parameters 10! ? good accuracy over
temperature 25C up to 150C ? unique
expression for different drain architectures
(p- n-channel XDMOS)
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• HV-DMOS MODELING

Two possible approaches
? COMPACT - modeling ? consider the device
unity ? Expression continuity in all regimes
of operations ? a set of self-consistent
expressions able to predict and reproduce
specific phenomena
? MACRO - modeling ? discrete elements tied
together to form a circuit (e.g. MOSFET, JFET,
diode, capacitor, Resistor etc.)
accuracy
parameters no extraction
?
?
?
simulation time
std. MOS drift model parameters
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• MODELING WITH EKV

Assumptions ? long-channel approximation
(i.e. short-channel effects are neglected)
? ?eff (i.e. simplified mobility
dependence on 2D field-effects)
Simplified expression
Complete expression
Strong-Inversion
Weak Strong-Inversion
Implicit expression
Can only be solved Numerically
Explicit expression
(2nd order polynomial)
Simple Analytical solutions
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? Strong Inversion expressions
Quasi-empirical drift expression
Charge expression
,
?
Effective mobility
Current expressions
?
Smoothing function (i.e. linear to saturation
transition)
?
Total current expression
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• MODEL PARAMETER

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• COMPACT- MODEL vs. MEASURES

? Fitted on a standard 4 ?m n-channel XDMOS
device, using the simplified drain expression.
ID-VD characteristics (TR)
gD(VD) _at_ VG
ID(VD) _at_ VG
For ID(VD) curves
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ID-VG characteristics (TR)
For ID(VG) curves
Errors calculated for G ? 3V
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• GLOBAL OPTIMIZING STRATEGY

• ? simplified ID formula ?? explicit
  expression ??
• ? since

Rdrift(VD) _at_ VG
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• The modelling strategy
• can be sequenced as follows

(i)  Performing standard extrinsic I-V
measurements on the HV DMOS transistor (ii)
Extracting VT and ?0 parameters (iii)
Calculating drift resistance characteristics
according to (iv) Fitting, with
the quasi-empirical drift expression the
calculated drift- resistance in
(iii) (v) Injecting the drift parameters,
together with the extracted VT and ?0 values,
in the simplified drain current expression
optimisation of the set of injected parameters
to fit the desired DC measured characteristics NO
TE In case weak and moderates inversions have to
be modelled, optimised parameters from (v) can be
used as initial guess values for the more complex
implicit expression of the drain current.
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• ADVANTAGES LIMITATIONS

• Model Advantages
• ? a total of (84) parameters for room
  temperature model
• ? simple and fast extraction of intrinsic
  MOS parameters (i.e. VT and ?0)
• ? a modeling strategy and an extraction
  procedure, independent on the MESDRIFT
• architecture
• ? a charge based model adequate and more
  convenient for AC modeling!

• Limitations
• ? limited accuracy in the weak inversion
  region (to be improved)

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• FUTURE DEVELOPEMENTS

? including the temperature dependence for the
intrinsic channel part (under
development) ? Replacing the simplified EKV
model by a more complete version (e.g. EKV
2.6) ? implementing model equations into
simulator using Verilog-A code (under
development) ? AC-modeling with a charge based
approach (under development) ? complete
model implementation into simulators (e.g. SPICE
or SABER)
Acknowledgements
This work was supported by the IST-1999-12257
AUTOMACS' EC project and the Swiss OFES no.
00-0009.
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