Robust%20FPGA%20Resynthesis%20Based%20on%20Fault-Tolerant%20Boolean%20Matching

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Robust FPGA Resynthesis Based on Fault-Tolerant
Boolean Matching

• Yu Hu1, Zhe Feng1, Lei He1 and Rupak Majumdar2
• 1Electrical Engineering Dept., UCLA
• 2Computer Science Dept., UCLA
• Presented by Yu Hu

Address comments to lhe_at_ee.ucla.edu
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Outline

• Background and Motivation
• Preliminaries
• Robust Resynthesis Algorithms
• Experimental Results
• Conclusion and Future Work

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Background

• Late CMOS scaling reduces device reliability
• Single event upset (SEU) due to cosmic rays
• Affects configuration SRAM cells in FPGAs
• Permanent soft error rate (SER)
• Need rewriting SRAM for recovery
• Affects combinational circuits and FFs
• Transient SER
• Can be recovered in multiple clock cycles

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Fault Tolerance Techniques for FPGAs
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Fault Tolerance Techniques for FPGAs
Our work
Low-cost, complementary approach to existing
techniques!
A. Djupdal and P. Haddow, Yield Enhancing Defect
Tolerance Techniques for FPGAs, MAPLD 2006
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Stochastic Synthesis and Logic Masking

• Stochastic synthesis assumes probabilistic logic
  values to model effect of random defects
• Break the conventional Boolean view which assumes
  deterministic Boolean 0 and 1 values
• Key to stochastic synthesis Logic Masking

Masked faults
0
1
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Stochastic Synthesis and Logic Masking (cont.)

• Stochastic Synthesis intelligently places logic
  masking.
• Logic Masking reduces the probability of the
  propagation of random faults
• Maximizes the stochastic yield
• However, logic synthesis to maximize yield rate
  w/o explicit redundancy and testing has not been
  studied for fault tolerance!
• Key questions
• How much does logic masking affect robustness?
• How and where to place logic masking?

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How much Logic Masking Affect Robustness?
Different synthesis leads to different logic
masking. Stochastic synthesis maximizes logic
masking!

• 18 synthesis solutions obtained by Berkeley ABC
• (for MCNC i10, LUT bit fault rate 0.1)

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How and Where to Place Logic Masking? Our
Major Contributions

• Propose a Robust FPGA resynthesis (ROSE)
• Maximize the stochastic yield rate for FPGAs
• No need to locate faults
• Use the same synthesis for different chips of one
  FPGA application
• Proposed a new PLB template for robustness
• ROSE Robust Template reduces fault rate by 25
  with 1 fewer LUTs, and increases MTBF by 31
  while preserving the logic depth
• compared to Berkeley ABC

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Outline

• Background
• Preliminaries
• Robust Resynthesis
• Experimental Results
• Conclusion and Future Work

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FPGA Synthesis Flow

• Attempt to re-map a logic block by Boolean
  matching
• Boolean matching can be used to handle both
  homogenous and heterogeneous PLBs

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FPGA Synthesis Flow (cont.)

• Multi-iterations of Boolean Matching-based
  Resynthesis

(Source Andrew Ling, University of Toronto,
DAC'05)
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Boolean Matching for Resynthesis
2-LUT
f
g
2-LUT
2-LUT
2-LUT
?
2-LUT

• Formulate the sub-problem of resynthesis to
  Boolean matching (BM)
• BM Can function f be implemented in circuit g ?
• Resynthesis Is there a configuration to g so
  that for all inputs to g, f is equivalent to g?
• Existing algorithms area/delay-optimal

(Source Andrew Ling, University of Toronto,
DAC'05)
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Outline

• Background
• Preliminaries
• Robust Resynthesis
• Problem Formulation
• FTBM Algorithm
• Robust PLB Template
• Experimental Results
• Conclusion and Future Work

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Modeling of Faults

• Model both faults in LUT configurations and the
  faults in intermediate wires as random variables,
  whose probabilities are given as inputs of our
  problem.

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ROSE Robust Resynthesis w/ FTBM

• Boolean Matching
• Inputs
• PLB H and Boolean function F
• Fault rates for the inputs and the SRAM bits of
  the PLB
• Outputs
• Either that F cannot be implemented by PLB H
• Or the configuration of H which minimizes the
  probability that the faults are observable in the
  output of the PLB under all input vectors.
• FTBM tasks breakdown
• Step 1 Find a Boolean matching solution
• Step 2 Evaluation the stochastic fault rate of a
  solution

• Fault-Tolerant Boolean Matching

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FTBM Step1 SAT Encoding for FTBM
Conjunctive Normal Form (CNF)

• If implementable, multiple configurations might
  exist
• The one with minimal fault rate is needed!

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FTBM Step2 Fault Rate Calculation Based on SSAT

• Simulation-based fault rate calculation
• Not scalable for multiple defects
• SAT-based fault rate calculation
• Intelligently modeling random defects

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SSAT Encoding for Fault Rate Calculation
Binary search is performed to find the maximal ß
Faults in intermediate wires
Faults in LUT configurations
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Example SAT-Based FTBM
g !x1!x3 !x2
abc g
000 1
001 1
010 1
011 0
100 1
101 1
110 0
111 0
PLB Template
Boolean function
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Example SAT-Based FTBM Step1 CNFs for the
PLB template
G LUT ( x1 x2 L0 z) ( x1
x2 L0 z) ( x1 x2 L1 z) ( x1
x2 L1 z) ( x1 x2 L2 z) ( x1
x2 L2 z) ( x1 x2 L3 z) ( x1
x2 L3 z)
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Example SAT-Based FTBM Step2 Replication
based on Truth Table
G G LUT1 G LUT2 G LUT3
abc g
000 1
001 1
010 1
011 0
100 1
101 1
110 0
111 0
Replication
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Example SAT-Based FTBM Step3 SAT Solving and
Mapping
SAT!
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Example SAT-Based FTBM Step4 Exploring More
SAT Solutions
Fault rate 0.2
Fault rate 0.3
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PLB Templates for SAT-based Resynthesis

• Area efficient templates A. Ling, DAC05
• Proposed robust template w/ path-reconvergence
• Can be configured by existing FPGAs

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Templates for SAT-based Resynthesis (cont.)

• Robust PLB template introduces more potential of
  dont-cares
• ROSE maximizes dont-cares iteratively at each
  template output

Observability dont-care
Satisfiability dont-care
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Outline

• Background
• Preliminaries
• Robust Resynthesis
• Experimental Results
• Conclusion and Future Work

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Experimental Settings

• Implementation in OAGear
• SAT-BM uses miniSAT2.0
• QUIP benchmarks are tested
• Are first mapped with 4-LUTs by Berkeley ABC
• Resynthesis settings
• One traversal is performed
• Blocks with up to 10 inputs are considered
• The fault rate of the chip is calculated by Monte
  Carlo simulation with 20K random vectors assuming
  the single fault
• Results are verified by ABC equivalency checkers

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Full-chip Fault Rate by Monte Carlo Simulation

• Fault rate is the percentage of input vectors
  that cause observable output errors assuming the
  single fault.

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Area (LUT)
ABC vs. ROSE/A vs. ROSE/R 1 0.9 0.99
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Estimation of Mean Time Between Failure

• SER modeling Mukherjee, HPCA, 2005
• Assume max-size FPGA 330,000 LUTs

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Outline

• Background
• Preliminaries
• Robust Resynthesis
• Experimental Results
• Conclusion and Future Work

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Conclusions and Future Work

• Developed ROSE and a robust template.
• ROSE is an orthogonal approach compared to
  existing fault-tolerant technique.
• Virtually no overhead on power, delay and area
• In the future, we will consider
• Multiple correlated faults,
• Alternative algorithms,
• Extension to standard cell-based circuits,
• Impacts on testability.

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• Robust FPGA Resynthesis Based on Fault-Tolerant
  Boolean Matching
• Yu Hu, Zhe Feng, Rupak Majumdar and Lei He
• University of California, Los Angeles

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Backup Slides
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Fault Characteristics of Templates Estimated
Based on Boolean Functions

• The minimal achievable fault rate
• The fault gap of template
• FTMB (min fault rate) vs. FTMB- (max fault rate)
• Fault gap Max fault rate - Min fault rate

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Fault Characteristics of Templates (cont.)
Estimated Based on Boolean Functions

• The minimal fault rates achievable by R-PLB are
  generally less than those achievable by A-PLB2.
• The fault gap of template R-PLB is generally
  wider than that of template A-PLB2
• There exists more flexibility to place
  don't-cares in R-PLB.

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Runtime
Resynth vs. ROSE/A vs. ROSE/R 1 3 10
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Background

• Late CMOS scaling reduces device reliability and
  increases both permanent and transient defects
• Major fault tolerance techniques for PLDs
• Triple Modular Redundancy (TMR)
• Manufacturer-masking
• Chip-wise Synthesis
• Precompiled Multiple Configurations

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Background

• Late CMOS scaling reduces device reliability and
  increases both permanent and transient defects
• Existing tolerance techniques for PLDs
• Triple Modular Redundancy (TMR)
• Manufacturer-masking
• Chip-wise Synthesis
• Precompiled Multiple Configurations
• However, logic synthesis to maximize yield rate
  w/o explicit redundancy and w/o testing has not
  been studied for fault tolerance!

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Motivation Example1 Boolean Matching vs. Fault
Tolerance

• g !b !a!c, mapped by 2-LUTs

gt20 difference!
Masked faults
0
1
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How does Logic Masking affact Robustness?
Logic masking in Boolean Matching

• g !b !a!c, mapped by 2-LUTs

0
gt20 difference!
Masked faults
0
1
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Full-chip Fault Tolerance

• ROSE/A ROSE with A-PLB
• ROSE/R ROSE with R-PLB
• 8 deterministic SAT-based resynthesis for area
  reduction

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Problem Formulation FTBM

• Inputs
• PLB H and Boolean function F
• Fault rates for the inputs and the SRAM bits of
  the PLB
• Outputs
• Either that F cannot be implemented by PLB H
• Or the configuration of H which minimizes the
  probability that the faults are observable in the
  output of the PLB under all input vectors.

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Fault Characteristics of Templates
Estimated Based on Full-chip
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Estimation of Mean Time Between Failure

• Source Mukherjee, HPCA, 2005, 330,000 LUTs
• Assumptions
• MTBF 109/(24x365) FITtotal
• FITtotal C x Vulnerability Rate x Intrinsic
  Error Rate
• Intrinsic Error Rate Area x FIT rate
• Vulnerability Rate Mean of fault rate
• FIT rate 0.01 FIT/bit, C 100