Ivo Bolsens

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• Ivo Bolsens
• Xilinx Research Labs

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Mission Statement

• Invent and discover technologies that create new
  business opportunities
• Track the external state-of-the-art and advise on
  the strategic implications of new technology
• Ensure that relevant internally- and
  externally-developed technology becomes a part of
  Xilinx's practice and products
• Participate in RD reviews, assist in product
  evaluations, and consult with all parts of Xilinx
  on issues related to technology
• Demonstrate to the technical and business
  communities that Xilinx is the technological
  leader in its space, is committed to remaining
  the leader, and controls its own technological
  destiny

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Research Programs
Dig Com
Multimedia
Networking
System Capture
Reconfigurable
Low Power
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Systems Applications

• Advance, capture observations about
• limitations of existing architectures
• suggestions for new architectural features,
  memory hierarchy etc.
• requirements for tools to support mixed HW/SW
  design flow, dynamic reconfiguration etc
• Understand and influence the relationship between
  algorithms, architecture and design methodology
  in selected leading-edge application domains
• DSP (image processing, soft radio) and Network
  processing
• Facilitate research into design technology at
  ever increasing levels of abstraction.
• Develop complex demonstration vehicles for use in
  evaluating new design methodologies and hardware
  architectures.

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Design Technology

• deliver innovative design methodologies, flows
  and tools
• in partnership with the product divisions
• that give Xilinx customers best-in-class
  solutions to their design challenges

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FPGAs are ahead of the curve
350
250
180
Process Technology Feature Size (nm)
150
130
100
70
97
98
99
00
01
02
03
04
05
Year
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A Decade of Progress
1000x
1000
Virtex-II
(excl. Block RAM)
100x
100
Capacity
Speed
Price
Virtex
Virtex-E
(excl. Block RAM)
XC4000
10x
10
Spartan
1
1x
1/91
1/92
1/93
1/94
1/95
1/96
1/97
1/98
1/99
1/00
1/01
Year
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FPGA Process Technology Leading the transistor
count in MOS Logic

• 2V6000
• 250 Million transistors per chip !
• 2V8000
• 360 Million transistors per chip !

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The Cost/Volume Crossover
1000
100
ASIC Cost
10
FPGA Cost
Relative Cost
1
0.1
10
100
1,000
10,000
100,000
1,000K
Unit Volume
10
Electronics Industry Dynamics
Residential Gateway (Broadband access)
Satellite/Cable Digital VCR
NTSC DES ATAPI DBS DOCSIS HomePNA HomeRF HomePLUG
Bluetooth Hiperlan2 DSL...
Digital VCR
Custom Features (Pay-Per-View)
Market Size ()
Dramatic increase in new standards
NTSC DES ATAPI DBS DOCSIS
Cable Decoders
NTSC DES ATAPI
NTSC Smart cards (DES)
NTSC

• New Products
• Take less time to reach high volumes
• Shorter Product Life Cycles
• Many standards / More Interoperability

Time
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Simpler/Faster Design Flows
Spec
Design and Verification
Silicon Prototype
System Integration
Silicon Production
ASIC Flow
Design Freeze
Spec
Design and Verification
System Integration
FPGA Flow
Design Freeze

• 21 proven Time-to-Market Advantage
• No silicon design or verification steps
• More design flexibility through later design
  freeze

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Todays Product Lifecycle
Profit for first to Market
Profit
Reduced profit for latecomers
Time

• 37 of new digital products were late to market
• Entering the market first can result in up to a
  40 greater total profit contribution over the
  products life vs. the 2 entrant

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Todays Product Lifecycle
IRL extends product life in market
Profit
Time

• 37 of new digital products were late to market
• Entering the market first can result in up to a
  40 greater total profit contribution over the
  products life vs. the 2 entrant

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Virtex-II Pro PowerPC Technology

• 32-bit RISC CPU, Harvard Architecture
• 130nm CMOS with 1.5V Operation
• 456 Dhrystone MIPS at 300MHz
• 32 x 32-bit General Purpose Registers
• Hardware Multiply / Divide
• 5-Stage Execution Pipeline
• 16KB D-Cache, 16KB I-Cache
• Memory Management Unit (MMU)
• High-Bandwidth Interface to Logic
• Built-In Hardware Timers
• Built-In JTAG Debug and Trace support

IBM PowerPC 405 RISC CPU
3.8 sq mm 1 of 2VP100
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High Performance
1824
1600
912
Dhrystone MIPS
800
456
400
220
200
1 CPU
100
AlteraExcaliburArm 9
Virtex-II ProPowerPC 405
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Where are we today
4
556
24
442
125K
10Mb
105K
340
168
3Mb
840Mb/sLVDS
3.125Gb/s MGTs
Multipliers
PowerPCCPUs
Logic Cells
Block RAM
XC2V8000 350M tranistors
XC2VP125
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Low PowerPC 0.59mW/MIPS
400
Full-Custom IBM CPU Design 1.5V 130nm CMOS
Technology Low-K Dielectric IP-Immersion
300
100mW 1 LED Indicator
Power (mW)
200
100
or 169 MIPS!
150
50
100
200
300
400
250
350
0
Performance (Dhrystone MIPS)
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IP-ImmersionEmbed multiple IP blocks of
arbitrary shape withhigh-bandwidth connectivity
to FPGA core logic, memory I/O

• Technologies Enabling IP-Immersion

Metal 9
Metal 8
Metal 7
Metal 6
Metal 5
Metal 4
Metal 3
Advanced hard-IP block (e.g. PowerPC CPU)
Metal 2
Metal 1
Poly
Silicon Substrate
Active InterconnectSegmented Routing
Metal Headroom
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HW/SW Interfacing

• Provides Specialized Connectivity Between PowerPC
  FPGA Logic
• Dual-Port BlockRAM Memory
• CPU Logic Each Own 1 Port
• High-Bandwidth
• 6.4Gb/sec
• Low-Latency
• Non-Caching
• Designed for Communications Data Processing
• Enables PowerPC FPGA Logic to Work together on
  Complex Problems

BlockRAMs
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System Level Design Flow
Enabling Technologies