Sassy Compiler

1
Sassy Compiler

• Wim Bohm
• Monica Chawathe
• Charles Ross

2
Software Architecture
RCS Code
Optimizations
SA-C
DDCF
DFG
AHA
VHDL
X86
C
Host Code
C
Data driven Simulation
RCS
PC
Verification
Timed Simulation
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Example

• Add two images A B
• SA-C Code
• uint32 main (uint32 A, uint32 B)
• uint8 R for a in A dot b in B
• return (array(ab))
• return (R)
• Data-flow Graph (DFG)
• Token Driven Simulation
• Abstract Hardware Architecture (AHA) Graph
• Timed (Synchronous) Simulation
• VHDL

4
DFG
1
1
0
0
ELE_GEN
ELE_GEN

1
TILE
5
AHA
TKGN
TKGN
1
1
CNT
CNT
RDWD
RDWD
1

CNT
1
WRWD
BUFX
6
AHA

• AHA Nodes
• Clocked Producer-Consumer State
• Clocked, no state
• Combinational
• Sections
• Producers
• ClockedState Nodes
• Consumers
• ClockedState Nodes
• Intermediate Nodes
• Clocked, no state and combinational

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Complex AHAs

• Non-word elements
• Ex uint8
• Fifo-Unpack
• Word to stream of pixels
• Follows Read-Word
• Window Generator
• Shift Register
• Width of window
• Stride
• 2-D Loop
• One token generator per loop dimension
• Innermost dimension
• Calculate word address
• Outer dimension
• Calculate row address

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VHDL

• AHA Nodes ? VHDL Component
• Token-Generator Entity
• entity TOK_GEN is
• generic (
• Bits integer 8)
• port (
• Clock in std_logic
• Reset in std_logic
• Ready_In out std_logic
• AllReady_In in std_logic
• Data_In in std_logic_vector(Bits-1 downto
  0)
• Ready_Out out std_logic
• AllReady_Out in std_logic
• Data_Out out std_logic_vector(0 downto
  0))
• end TOK_GEN

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VHDL (contd.....) Archetecture

• CountZero lt '1' when Count 0 else '0'
• Data_Out(0) lt CountZero and HaveVal
• Ready_In lt not HaveVal
• Ready_Out lt HaveVal
• TProc process (Clock, Reset)
• begin
• if Reset '1' then
• Count lt (others gt '0')
• HaveVal lt '0'
• elsif Clock'event and Clock '1' then
• if AllReady_Out '1' then
• Count lt Count - 1
• if (CountZero '1') then
• HaveVal lt '0'
• end if
• end if
• if AllReady_In '1' then
• Count lt Data_In
• HaveVal lt '1'