Rahul Kodkani,

1
Rahul Kodkani, Prof. L. E. LarsonDepartment of
Electrical and Computer Engineering Jacobs
School of Engineering, University of California
San Diego, CA 92093
Silicon-based Mil limeter Wave Transceiver
Circuits for 60 GHz GBPS Wireless Communications
Motivation
60 GHz LNA in IBM 8HP BiCMOS Process
30 GHz Two Stage Ring Oscillator

• Two Stage Differential Cascode LNA
• Microtstrip lines with M1 ground plane used for
  matching
• Small valued ( 15 fF) fringe capacitors to
  resonate bond-wire inductance
• Microstrip line based inductors (slab inductors)
  used to tune out bond-pad capacitance

Power Amplifier
Frequency Quadrupler
Two Stage Ring Oscillator
Mixer
Low Noise Amplifier

• Quadrature Generation for Subharmonic Mixers
• RC polyphase filters
• amplitude and phase inaccuracies
• sensitive to parasitics
• 90 degree hybrids
• take up lot of area at 30 GHz
• Ring oscillator
• can provide accurate multiple phases

Transceiver Building Blocks in PHEMT process
Power Amplifier

• GBPS wireless data rates are achievable in the
• 59 64 GHz Frequency Band
• Existing Solutions use expensive hybrid GaAs
  technology
• Can we build these in Silicon?
• Can we move from expensive technologies to low
• cost silicon similar to what cellular phones
  witnessed?

Layout of the 60 GHz LNA
Low Noise Amplifier
Source K. Fujii, M. Adamski, P. Bianco, D.
Gunyan, J. Hall, R. Kishimura, C. Lesko, M.
Schefer, S. Hessel, H. Morkner, A. Niedzwiecki,
A 60 GHz MMIC chipset for 1-Gbit/s wireless
links, IEEE MTT-S Digest, pp. 1725-1728, 2002.
Simulation Results Low Noise Amplifier
Project Goals
Delay Cell schematic
Layout of the Ring Oscillator
Typical simplified Superheterodyne Receiver

• Gain is gt 16 dB
• Noise Figure of 8.8 dB

Comparison of various technologies available
Typical simplified Homodyne Transmitter

• Design and implementation of integrated low-cost
  SiGe MMWIC transceiver building blocks for Gbit/s
  wireless data rates

Performance Summary (post layout simulations)
Performance Summary (post layout simulations)
Summary and Future Work
Performance Summary
60 GHz Subharmonic Mixer
60 GHz Low Noise Amplifier

• Summary
• 16 dB S21, 8.8 dB NF, 60 GHz LNA designed and is
  back from fabrication
• 30 GHz Two Stage Ring Oscillator with 83 dBc/Hz
  phase noise _at_ 1 MHz offset has been taped out for
  fabrication
• Future Work
• Integrated Downconverter with Ring Oscillator
• Integrated Receiver to receive GBPS data
• Power Amplifier with Power Combiner

• Need For Subharmonic Mixers
• Can avoid DC offsets due to LO Self Mixing in
  Direct Conversion Receivers
• LO generation is easier since it is a
  subharmonic fraction of the RF frequency

• Simulation Results (schematic)
• Conversion Gain 13 dB
• Noise Figure (SSB) 10.5 dB
• Supply Voltage 3.3V
• DC Current Consumption 7 mA

Simplified schematic of the LNA (half)
Differential Cascode LNA

• Differential Topology for easing grounding
  requirements
• Bondwire inductance resonated out with fringe
  capacitors
• Bondpad capacitance resonated out with line
  inductors

• Two stages to give enough gain
• First stage optimized for noise
• Second stage optimized for gain

Schematic of the Subharmonic Mixer