Section 4 Register Files and Arithmetic Units

1
Blackfin Presentation SHARC Users Group March
2003
by Joerg Hauber (FAE)
2
Target Applications Internet Era of Signal
Processing

• PDAs Digital Still Cameras Video
  Cameras Digital Printing
• Internet Audio Video Conferencing
  Internet Appliances Mobile Phones
• Cable Modems Telephony
• Integrated Access Devices Modem PABX
• Voice over Network Recognition
• Handwriting Recognition Text to Speech
• Speech to Text Echo Cancellation
• Imaging Portable Medical
• MP3 Audio DVD playback
• MPEG2 Video Conferencing Surround Sound
  Audio
• 3G Data Terminals Speakerphones
• Car Infotainment Consumer Audio
• Set top Box Home Networking
• Modems GPS
• VoIP Phone Solutions ADSL Modems Car
  Digital Radios Navigation systems
  Automotive security ADSL Modems Digital
  Car Radios
• RAS modems Web Pads Wireless Modems
  GSM Phones

3
User Benefits

• High Performance
• BLACKfin?DSP offers 600MMAC performance today
  with roadmap to 2GMAC.
• Low Power Consumption
• BLACKfin? DSP enables significant power savings
  by dynamically varying both operating frequency
  and voltage.
• Easy to Use
• BLACKfin?DSP combines attributes of both high
  performance DSPs and microcontrollers into a
  single RISC device.

4
Controls Voltage Frequency

• Multiple Power-Down modes
• Functional Peripheral blocks can be clocked
  only when used

Optional Power managment IC regulates voltage
ADP 3053

• Dynamic Power Management using RTOS or Firmware
• Profiling Tools audit MIPS requirements by
  function

5
Blackfin DSPs Optimize Power Consumption
Vdd
1.5V, 300MHz
DSP Operation
t
1.3V, 225MHz
PLL Settling
DSP Operation
1.0V, 100MHz
PLL Settling
Regulator Transition
DSP Operation
Regulator Transition
Power Consumption
Just vary the frequency
Dynamic Power Management
Vary the voltage and frequency
6
Integrated Blackfin Features Typically Found in a
Micro-Controller
and
A RISC Instruction Set
Data Movement LD, ST, 8,16,32 bits Unsigned,
Sign-extend Register moves, P-D-DAG, Push, Pop,
Push/Popmult CC2 dreg, etc. Addressing
Modes Auto incr, Auto decr, Pre-decr store on
SP, Indirect Indexed w/immed offset Post-incr w/
nonunity stride Byte addressable Program
Control BRCC, UJUMP, Call, Rets, Loop Setup
Arithmetic ,-,,/,gtgtgt, Negate 2 and 3 operand
instructs Logical AND, OR, XOR,
NOT BITtst,set,tgl,clr, CC ops ltlt,gtgt Video SAA,
Byteops Residual calc, Spatial Interpolation,
Spatial Filter Cache Control Prefetch, Flush
Memory management
Event control
Supervisor/user modes
Wide range of peripherals
There is not a separate Micro-Controller mode!
7
Operating Modes

• Supervisor mode
• Emulator/Debug mode
• User mode

Application Code
User
RTI, RTX
Emulation Event
Interrupt or Exception
RTE
Emulation Event
Supervisor
Emulation
RTE
System, Code and Event Handlers
8
Micro Signal Architecture Core

• Two 16-bit Multipliers
• Two 32/40-bit ALUs
• Four 8-bit Video ALUs
• Barrel Shifter
• Sixteen 16-bit Math registers /
• Eight 32-bit Math Registers
• Two DAGs, byte addressing
• Eight 32-bit pointer registers
• Four Sets of 32-bit Index,
• Modify, Length, Base
• 16-bit Instructions
• 32-bit Instructions
• Multi-Issue, 64-bit Instructions

Blackfin ? DSP Core based on the Micro Signal
Architecture Jointly Developed With Intel
Corporation
9
Register View of Math
Dual ALU / MAC functions are Vector
functions Two Pairs of operands are available
16
0
31
R2
31
16
0
R3
32
32
Register File
MAC 0 ALU 0
MAC 1 ALU 1
A0
A1
R6
R7
32
32
10
Arithmetic Logic Unit (ALU)

• Two ALUs operating on 16-bit, 32-bit, and 40-bit
  input operands and output 16-bit, 32-bit, and
  40-bit results.
• Functions
• Fixed-point addition and subtraction
• Addition and subtraction of immediate values
• Accumulator and subtraction of multiplier results
• Logical AND, OR, NOT, XOR, bitwise XOR, Negate
• Functions ABS, MAX, MIN, Round, division
  primitives
• Features
• Supports conditional instructions
• 8-bit video ALU operations

11
Multiply-Accumulators (MAC)

• Two identical MACs
• Each can perform fixed point multiplication and
  multiply-and-accumulate operations on 16-bit
  fixed point input data and outputs 32-bit or
  40-bit results depending the destination.
• Functions
• Multiplication
• Multiply-and-accumulate with addition (optional
  rounding)
• Multiply-and-accumulate with subtraction
  (optional rounding)
• Dual versions of the above
• Features
• Saturation of accumulator results
• Optional rounding of multiplier results

12
Barrel-Shifter (Shifter)

• The shifter performs bitwise shifting for 16-bit,
  32-bit or 40-bit inputs and yields 16-bit,
  32-bit, or 40-bit outputs.
• Functions
• Arithmetic Shift The Arithmetic Shift
  instruction shifts a registered number a
  specified distance and direction while preserving
  the sign of the original number. The sign bit
  value back-fills the left-most bit positions
  vacated by the arithmetic right shift.
• Logical Shift The Logical Shift instruction
  logically shifts a registered number a specified
  distance and direction. Logical shifts discard
  any bits shifted out of the register and backfill
  vacated bits with zeros.
• Rotate The Rotate instruction rotates a
  registered number through the CC bit a specified
  distance and direction.
• Bit Operations
• Field Extract and Deposit

13
Data Types

• 8-bit bytes
• signed or unsigned integers
• 16-bit half-words (little Endian)
• signed or unsigned integers
• signed fractional (1.15)
• 32-bit words (little Endian)
• signed or unsigned integers
• signed fractional (1.31)

14
8 bit Video Alu
15
Video pixel operations

• ALIGN8,16,24 (align data in src_reg)
• BYTEPACK (Quad 8-bit Pack)
• BYTEOP16P (Quad 8-bit ADD)
• BYTEOP16M (Quad 8-bit Substract)
• BYTEOP1P (Quad 8-bit Average Byte,ADD/DIV2)
• BYTEOP2P (Quad 8-bit Average Half word,
  ADD/DIV4)
• BYTEOP3P (DUAL 16-Bit ADD word and byte / Clip
  to byte)
• BYTEUNPACK (QUAD 8-bit Unpack)

16
BYTEOP16P

• BYTEOP16P (Quad 8-bit Add)
• Adds eight unsigned bytes to result in four
  16-bit words
• General Form
• (dest_reg_1, dest_reg_0) BYTEOP16P(src_reg_0,
  src_reg_1)
• source data chosen by I0 from register pairs R32
  and R10
• Example
• (r1, r2) BYTEOP16P(r32, r10)

17
Quad-Byte Averaging (1)

• BYTEOP1P (Quad 8-bit Average Byte)
• Averages four unsigned byte pairs to produce four
  8-bit results
• General Form
• dest_reg BYTEOP1P(src_reg_0, src_reg_1)
• source data chosen by I0 from register pairs R32
  and R10
• Example
• r3 BYTEOP1P(r10, r32)

18
Quad-Byte Averaging (2)

• BYTEOP2P (Quad 8-bit Average Half-Word)
• Averages two unsigned byte quadruples to produce
  two 8-bit results
• General Form
• dest_reg BYTEOP2P(src_reg_0, src_reg_1)
• source data chosen by I0 from register pairs R32
  and R10
• Example
• r3 BYTEOP2P(r10, r32)

19
4-Neighborhood Average

• The value of the center pixel is defined like
  this
• x (xNxSxExW)/4
• A better description is
• x average(xN, xS, xE, xW)
• BYTEOP2P can perform this kind of average on two
  pixels in 1 cycle

20
Quad-Byte-Sum Absolute Difference (1)

• SAA (Quad 8-bit Subtract-Absolute-Accumulate)
• Subtracts four pair of bytes, takes the absolute
  value of each difference, and accumulates each
  result into a 16-bit accumulator half
• N is typically 8 or 16 (corresponding to blocks
  of 8x8 and 16x16 pixel, respectively)
• Useful for block-based video motion estimation

21
Configurable Memory System

• Supports a Cache Memory Model and an SRAM Memory
  Model
• Sustained Dual Data Accesses for DSP Applications
• Supports accesses of 8, 16, 32 bit Data
• Separate Multi-ported L1 Instruction and Data
  Memories

L2 Instruction Data SRAM
L1 Instruction SRAM Cache
Processor Core
L1 Data SRAM Cache
Scratchpad SRAM
DMA
22
21535 Memory Levels

• Internal L1 memory -
• Closest to the Processor
• Can be configured as cache or SRAM
• Smallest Memory Capacity(16KB Instruction, 36KB
  Data)
• Single Cycle Access
• Internal L2 memory -
• Further from the Processor
• Larger Memory Capacity (256KB Total for
  Instruction/Data)
• Multiple Cycle Access
• External L2 memory -
• Off Chip
• Largest Memory Capacity (Synchronous and
  Asynchronous)
• Slowest access time

23
Direct Memory Access

• The ADSP-21535 DMA controller allows data
  transfer operations without processor core
  intervention
• Types of data transfers
• Memory Memory (MemDMA)
• Memory Serial Peripheral Interface (SPI)
• Memory Serial Port
• Memory UART Port
• Memory USB Device

24
Instruction Set Optimized for Rich Media
Applications

• Video Applications
• Up to four 8-bit math operations in a single
  cycle
• DCT / iDCT Support (Less than 300 cycle 88 DCT)
• Dual MAC with IEEE 1180 Rounding
• Motion Estimation
• Quad-Byte Operations (e.g. Sum Abs. Differences)
• Huffman Coding
• Sophisticated Field Deposit / Extract Capability
• 2G and 3G Communications Protocol Standards
• Voice Codecs On-The-Fly Saturation Arithmetic
• Channel Codecs Instruction Set Support for
  Complex Math, Bit Interleaving, Population Count,
  Viterbi Dual Add-Compare-Select, and CRC

25
Performance

• DSP Code is often a C - language program with
  interspersed assembly code Kernels. The measure
  of performance is threefold
• The Compiled Program Code Size - measure of Cost
  and Power Consumption
• The Compiled Code Performance - measure of Power
  Consumption and Software Engineer Work remaining
  (TTM )
• The Assembly Level Kernel Performance - measure
  of Power Consumption

26
Optimized DSP Software Libraries Currently In
Development
www.analog.com -gt Digital Signal Prozessing -gt
Blackfin -gt Code Examples

• Image Processing Libraries
• Generic Pixel Interpolation Algorithms
• Auto Focus, Auto Exposure Control
• Auto White Balance
• Color Space Conversion, RGB ? YCrCb
• Transformations, 4.4.4 ? 4.2.2, 4.2.2 ? 4.2.0,
  4.4.4 ? 4.2.0
• Image Processing Application Development
• Bilinear Interpolation Image Processing
• Linear Laplace Interpolation Image Processing
• High Quality Image Processing
• Video Image Processing
• Image/Video/Audio Processing CODECs
• Still - JPEG, JPEG2000
• Audio - MP3, AAC, MPEG1 layer 2 audio
• Video - MJPEG, MPEG2, MPEG-4

27
ts - OS 3rd Party Partners

• Nucleus and Nucleus uITRON from Accelerated
  Technology ( http//www.acceleratedtechnology.com
  )
• Embedded Linux from Embedix ( http//www.embedix.
  com )
• CMX from CMX (http//www.cmx.com )
• Real Time Architect from LiveDevices (
  http//www.livedevices.com )
• ThreadX from Express Logic ( http//www.expresslo
  gic.com )
• DSP OS from DSP OS ( http//www.dspos.com )
• VspWorks from WindRiver ( http//www.windriver.co
  m )
• uC Linux from Lineo ( www.lineo.com )
• LiveDevices Limited ( www.livedevices.com )
• KwikNet TCP/IP Stack Kadak (www.kadak.com)

28
Video Technology Third Parties
29
ADSP-21535 t TargetsVideo-Enabled Internet
Appliances
Performance
600MMACs 306 DhrystoneMIPs
640mW, 300MHz 100mW, 100MHz
Power _at_ 1.5V _at_ 0.9V
Dynamic Power Management Varies Frequency And Vol
tage
2.4 Gbyte Per Second I/O Band- Width
768Mbytes
Address Range
48K bytes
Instruction / Data Cache
300 MHz 16-bit Fixed-Point Core
260Kbytes
On Chip SRAM
PCI USB Device 2 SPORTS 2 UARTS 2 SPI 3 32-bit
Timers
Peripherals
Interfaces To External FLASH And SDRAM
308 Kbytes On-Chip SRAM
0.9V to 1.5V
Voltage
260 PBGA
Package
Memory Subsystem
Part Number
ADSP-21535
30
ADSP-21535
System Peripherals
User Peripherals
Dynamic Power Mgmt.
PCI Interface
PLL
Watchdog
16K byte
32K byte
4K byte
JTAG
256K bytes SRAM 300MHz
Interfaces
FLASH SRAM
USB Device
Memory Subsystem
SDRAM
31
ADSP-21532 t TargetsCost-Sensitive Consumer
Applications
Performance
300MHz 600MMACs
132Mbytes
Address Range
Dynamic Power Management Varies Frequency And Vol
tage
2.4 Gbyte Per Second Memory Band- Width
84K bytes
On-Chip RAM
32Kbytes
On Chip ROM
300 MHz 16-bit Fixed-Point Core
2 SPORTS UART SPI 3 Timers Parallel Peripheral
Interface/GPIO
Peripherals
Interfaces To External FLASH And SDRAM
84 Kbytes On-Chip SRAM
2.25V to 3.6V
Voltage
160 Mini-BGA
Package
Memory Subsystem
ADSP-21532
Part Number
32
ADSP-21535 Availability

• Development Tools Availability Date
• - Visual DSP IDE Today
• - EZ-ICE and EZ-KIT Today
• Documentation
• - Data Sheet Today
• - HW/SW Reference Guides Today
• Silicon
• Samples Today
• Production Q1 2003
• Pricing
• ADSP-21535PKB-300 25 _at_ 10K
• ADSP-21535PKB-200 22 _at_ 10K

Please visit http//www.analog.com/blackfin-dsp
for additional information!!!
33
ADSP-21532 Release Plan

• Tools Availability Date
• VDSP Upgrade Now
• EZ-KIT, ICE CY 1Q 03
• Documentation
• Data Sheet Now
• Hardware Reference Now
• Silicon
• Samples Now
• Production CY 4Q 03
• Pricing
• ADSP-21532SBBC-300 9.95 _at_ 10K

34
Ordering Guide and Specifications
Packages
Speed
Temp(Case)
ROM
SRAM
Part Number
260 -PBGA
300 MHz
0C to 85C
Boot
308K Bytes
ADSP-21535PKB-300
-40C to 105C
260 -PBGA
200 MHz
Boot
308K Bytes
ADSP-21535PKB-200
-40C to 105C
300 MHz
32K Bytes
84K Bytes
ADSP-21532SBBC-300
160 miniBGA
35
ADSP-21532 Differences
36
ADSP-21532 Consumer Multimedia Enhancements

• Highly integrated peripheral set reduces BOM
  costs
• PPI supports CCIR-656 video converter interface
• Enhanced serial ports support up to 8 stereo I2S
  channels
• 2-D DMA supports data transfer with programmable
  count stride values

37
Parallel Peripheral Interface
External Clock
PPICLK SYNC
Appliances
Up To 16-bit Parallel Data

• Bidirectional, half-duplex interface
• Supports CCIR-656 Video Converter Interface
• PPI provides general fast ADC / DAC interface at
  up to 65MSPS

38
PPI - Features

• Can optionally ignore Field 2 (dont DMA)
• Works hand-in-hand with ADSP-21532 2D DMA Engine
• Can skip even or odd data elements
• Supports 16-bit data packing mode
• Supports 32-bit DMA mode (2 bursts of 16-bit DMA)
• 4 control signal polarity choices (H,V,CLK)

39
PPI I/O Modes
PPI
8- or 10-bit data w/embedded control
PPIx
CCIR-656
656-Compatible Video Source
CLK
PPI_CLK
HSYNC
GP - Mode
PPI_FS1
VSYNC
PPI_FS2
Video Source
FIELD
PPI_FS3
PPI
8-16 bits data
PPIx
CLK
PPI_CLK
40
Possible Data Transfer Scenarios
Video Data and Control
L1 Memory
DMA
DMA
SPORT
PPI
Compressed Video
DMA
DMA
L1 Memory
PPI
SDRAM
DMA
External Processor
SPORT
41
2-D Direct Memory Access
2-D DMA significantly accelerates video processing
Programmable X Y Count Stride Values
Linear Data Capture Storage
A
A
F
D
E
G
C
B
H
B
C
N
K
P
O
M
L
J
I
D
E
2-D DMA to L1 Memory
F
A, B, I, J
G
H
I
J
K
L
.
.
.
.
42
Serial Ports

• Two Dual-Channel Synchronous Ports supporting 8
  Stereo I2S Channels
• Supports 3-32bit data widths
• 100MHz operation from external clock
• SCLK/2 operation from internal clock ( up to
  66MHz )

Primary TX Secondary TX Tx Clock Tx Sync
Primary Rx Secondary RX Rx Clock Rx Sync
43
ADSP-21532 in Prosumer Audio

• 32-Bit Math
• 31 x 31 Audio Multiply in 2 cycle loop ? 150MHz
  (effective)
• 32 x 32 Multiply in 3 cycle loop ? 100MHz
  (effective)
• Serial Ports
• Eight Stereo I2S Channels
• Programmable L/R channel
• Up to 100MHz operation
• Application Areas
• Digital Mixers, Home Theatre, Car Audio

44
Memory Interface
1M Byte Asynchronous
16K Bytes Instruction SRAM/Cache
1M Byte Asynchronous
32K Bytes Instruction SRAM
1M Byte Asynchronous
1M Byte Asynchronous
32K Bytes Instruction ROM
16
External Memory Interface
32K Bytes Data SRAM/Cache
16M Byte 128M Byte Synchronous
4K Bytes Scratchpad SRAM
45
Power Management--Variable Voltage

• On-chip Voltage Regulation
• Generates core voltage from external 2.25V to
  3.6V input
• Core voltage programmable in 50mV increments
• Optional bypass
• Minimal external components required

D
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V
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46
Dynamic Power Management - Variable Frequency
Dynamically Modification On the fly
Dynamic Modification Requires PLL Sequencing
? 1, 2, 4, 8
CCLK
CLKIN
PLL 1x - 31x
? 1 15
SCLK
SCLK
SCLK lt CCLK SCLK lt 133MHz
CCLK
PLL
47
New Blackfin DSPNDA information
48
BLACKfin DSP NDA Roadmap
Blackfin DSP
Blackfin DSP Teton (dual Core)
21533 600MHz
Video and High Performance
Blackfin DSP
Blackfin DSP 500MHz/Nx
21532 300MHz/10
Performance/Price
21535 300MHz
Network and Communications
2002
2003
lt 2001
2004
49
BLACKfin DSP New ADSP-21533 Brief Summary

• ADSP-21533 Blackfin DSP will be sampling in 1Q03
  at the highest clock rate of any commercially
  available GP DSP Product.
• Blackfin DSPs will demonstrate 3x speed of the
  available competitive architectures in its class.
• ADSP-21533 Blackfin DSPs high speed and Dynamic
  Power Management are ideal for high performance
  (video) portable applications.
• Blackfin DSPs are the platform on which many new
  ADI system level products are being built,
  including Vehicle Telematics and Wireless
  Communications.

50
BLACKfin DSP ADSP-21533 Architecture Overview
48KB Instruction SRAM/ Cache
System Control Blocks
Memory DMA
Emulator Test Control
Voltage Regulation
Event Controller
Clock (PLL)
Watchdog Timer
RealTime Clock
Processor Core 600MHz
External Memory Interface FLASH SRAM SDRAM
64KB Data SRAM/ Cache
16KB Instruction Cache
4KB Scratchpad RAM
64KB Instruction SRAM

System Interface Unit
ITU-R 656 Video Interface (PPI)
Timers 0/1/2
SPORT0
SPORT1
UART
SPI
Peripheral Blocks
51
BLACKfin DSP ADSP-21532 and ADSP-21533 Memory
Maps
52
BLACKfin DSP ADSP-21533 and ADSP-21532

• ADSP-21533 is a Larger Memory, higher
  performance , pinpin compatible part to the
  ADSP-21532

ADSP - 21532
ADSP - 21533
ADSP - 21533
Performance
300 MHz, 600 MMACs
500 MHz, 1000 MMACs
600 MHz, 1200 MMACs
Address Range
132MBytes
132MBytes
132MBytes
On Chip RAM
84KBytes
148KBytes
148KBytes
On Chip ROM
32KBytes
-
-
Price at 10Ku
9.95
17
23
53
BLACKfin DSP ADSP-21533 Power Consumption

• New Blackfin targets derived from ADSP-21535
  factual data
• ADSP-21535 consumes 640mW at 300MHz at 1.5V
• Scaling to 1.0V and applying 30 further
  reduction expected from geometry ( 0.18u to 0.13u
  ) , reduced gate capacitance and custom
  implementation methodology.
• ADSP-21533 Power Targets
• Less than 350mW at 500MHz at 1.0V
• Less than 100mW at 200MHz at 0.7V

54
BLACKfin DSP for Portable ApplicationsDynamic
Power Management Benefits

• Blackfin DSPs offer the highest DSP performance
  for applications that require it
• MP3PRO Encoding
• CIF Video Conferencing
• AND the same device delivers the lowest power
  consumption when the demands reduce
• MP3 Decoding
• Speech Recognition
• Text to Speech

mW
MHz
55
BLACKfin DSP - ADSP-21533 Example Video
Display System

• Single chip Audio and Video Decoder for
  Entertainment System
• Video transport over local bus, connected through
  SPORT0 and SPI control
• SPORT1 connects to stereo speakers and
  microphones
• MPEG2 Video Decoding
• MPEG2 Audio Decoding
• Speech Recognition command and control with noise
  canceling array microphone input
• Reduced existing BOM by gt50

SPORT0
SPI
ADSP-21533
CIF Display
PPI
SPORT1
FLASH
SDRAM
56
BLACKfin DSP - ADSP-21532 Example Low Cost
Video Surveillance

• Single chip Video Encoder for surveillance
  systems
• Video capture example Omnivision integrated
  lens / sensor
• SPORT1 connects microphone
• MPEG4 CIF Video Encoding
• MPEG4 Audio Encoding optional
• Video transport over Ethernet or SPORT
• Reduced existing BOM by gt60

ADSP-21532
Capture Sensor
SPORT0
PPI
L A N
SPORT1
FLASH
SDRAM
57
BLACKfin DSP - ADSP-21533 Example Low Cost
Video Display

• Single chip Video Decoder for Portable Display
  systems
• Video Display through PPI
• SPORT1 connects Speakers
• MPEG4 CIF Video Decoding
• MPEG4 Audio Decoding optional
• Content transport over WLAN
• Reduced existing BOM by gt50

ADSP-21533
CIF Display
PPI
SPORT1
802.11
FLASH
SDRAM
58
BLACKfin DSP ADSP21532 ADSP21533 Release Plan

• Silicon
• ADSP-21532 Samples 1Q03
• ADSP-21533 Samples 1Q03
• Production CY Q403
• Pricing
• ADSP-21532SBCA-300 9.95 _at_ 10K
• ADSP-21533SBCA-300
• ADSP-21533SKCA-500 17 _at_ 10K
• Tools
• VDSP Upgrade Now
• EZ-KIT, ICE CY 1Q 03
• Sales Collateral
• Preliminary Data Sheet Now, on Web
• Hardware Reference Manual CY 4Q 02

59
Blackfin DSP ADSP-21533 - MPEG4 Processing
Capability

• Hardware Facilitators
• Parallel Peripheral Interface
• 2-D DMA
• CCIR-656 SOL/SOF support
• Application Areas
• Video-Enabled Information Appliance, Security
  Systems, Videophone

70 core loading
60
Blackfin DSP ADSP-21533 - DVD Decoding MPEG2
95 Loaded
50 Loaded
31 Loaded
52 Loaded
13 Loaded
61
Blackfin DSP Image Decode Performance

• JPEG2000
• 140 cycles/pixel 422 decode
• 2Mpel requires 280 MHz
• JPEG
• 39 cycles/pixel 420 Encode
• 2Mpel requires 80 MHz

62
BLACKfin DSP Roadmap
Portable Image / Video
Blackfin DSP (Video)
1400
Blackfin DSP (Video)
Blackfin DSP PCI / Ethernet
1000
Blackfin DSP USB / Ethernet
Performance MHz
ADSP-21533 Reg / CCIR656
500
ADSP-21532 Reg / CCIR656
ADSP-21535 PCI / USB
Internet / Network
300
2004
2003
2001
2002
63
BLACKfin DSPLong Term Roadmap

• Technology Advances
• Further the availability of interfaces on
  products USB 2.0, Ethernet, Bluetooth
• Further availability of memory derivatives and
  higher speeds
• Provide commercial, Industrial and Extended temp
  range products
• Add software partners that help Blackfin to
  absorb simple microprocessor tasks

64
Digital Imaging Products

• ADSP-21535 - Sampling NOW
• First implementation of MSA (Blackfin) core
• 300Mhz, 600MMACs performance
• CIF MPEG2 Encoder or Decoder MPEG4 simple
  profile
• ADSP-21532, ADSP-21533 - Sampling 1Q03
• 300MHz and 500Mhz, performance
• Low Power designed for portable consumer
  applications
• Video peripherals
• Video Interface supporting input/output of
  CCIR656 signals etc.
• CIF MPEG2 Encoder and Decoder MPEG 4 Advanced
  Simple Profile Encode and Decode, JPEG
• Dual-core - Under Design Sampling 2H03
• Dual 500MHz processor cores, dual Video
  Interfaces
• Storage (ATA Interface), LCD controller, (
  Ethernet MAC) , USB, Additional Serial Comms
• VGA MPEG2 Encoder Decode MPEG4, JPEG
• Next Generation Digital Video/Imaging Products
  (To be defined)
• 1 GHz roadmap, multicore roadmap

65
Next Generation Video Processor (Teton lite)
System Peripherals
User Peripherals

• Targets High-Performance Video Applications
  Security/Surveillance, Broadband Home Gateways
• Dual 500 MHz Cores , 1000MHz/2000 MMACs
• 200KBytes L1 Memory
• 128KBytes L2 Memory
• TSMC 0.13um, 5LM

Dynamic Power Management
Upgraded SPORTs 2
Switching Regulator
SPI 1
32K Bytes
64K Bytes
4K Byte
UART 2
PLL
128KByte L2
Watchdog (2)
JTAG
Timers 12
4K Byte
64K Byte
32K Byte
GPIO 32
Interfaces
FLASH/SRAM
2 Video I/O and DMA
SDRAM
66
BlackfinDSP plus Network Connectivity

• Targets simple connected DSP applications
• Single 500 MHz Core, 500MHz/1000 MMACs
• Integrated Ethernet and USB connectivity
• TSMC 0.13um, 5LM

67
BLACKfin DSP Portable Video DSP Roadmap
LCD Controller
Emulator Test
Dynamic Power Management
Video Capture
Video Display
Blackfin Processor Core
Blackfin Processor Core
128kByte Image Buffer
80kByte Instruction
80 kByte Instruction
68 Kbyte Data
68 kByte Data
FLASH, SRAM, SDRAM Memory Interface

ATA Interface
I2S Audio Converter Interface
Timers GP IO
I2C
SPORT1
UART
SPI