Platform Based Analog Design

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(No Transcript)
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Mixed Signal Design Space Exploration through
Analog Platforms

• F. De Bernardinis??, P. Nuzzo?, A. Sangiovanni
  Vincentelli?
• ?UC Berkeley
• ? University of Pisa, Italy

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Outline

• Introduction
• Analog Platforms
• definition
• design flow
• Performance Models
• definition
• optimization of approximation process
• Mixed-Signal Case Study
• pipeline ADC design with platforms
• optimization and results
• Conclusions

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Introduction

• Mixed-Signal Design
• heterogeneous problem to be coped at system level
• most remunerative tradeoffs across A/D interface
• scant attention in the past
• Platform Based Design
• originates as an answer to engineering and
  economic issues
• widely accepted in the design community
• moves design focus to composition of library
  elements
• Analog Design Flows
• limited synthesis capabilities
• struggle with device and circuit complexity

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Platform Based Design

• PBD is a meet-in-the-middle recursive process

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Analog Platforms Definitions

• An Analog Platform is a library of components
• Platform Component Abstraction
• input/output domains
• behavioral model
• feasible performance model
• validity laws
• The set of feasible performance models is
  described as
• abstract configuration parameters

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Analog Platforms Definitions

• Example level 0 OTA
• U0 is the set of Vin(t)
• Vin lt 100 mV, fmax 2 MHz
• K0 is the set of MOS sizings
• X0 is the set of internal V and I
• Y0 is the set of Vout(t), gain, IIP3, rout
• F0 is the solution of device equations
• e.g. Spectre simulation
• L0 is obtained from Kirchhoff laws andmaximum
  device ratings

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Analog Platforms Definitions

• Example level 1 OTA
• U1 U0
• X1 x1, x2, x3
• Y1 is the set of Vout(t)
• F1 is given by
• L1 is empty
• K1 is the set a1, a3, f-3dB, noise, rout
• K1 and Y0 are strongly related
• in this case, K1 is a simple projection of Y0

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Analog Platforms Definitions

• Platform Instance
• Composition of plat-form components
• Defined by
• h ? H, ? ??
• ? ? ?, ? ? Z
• behavioral model G
• composition constraints

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Analog Platforms Definitions

• Platform Instance
• Composition of plat-form components
• Defined by
• h ? H, ? ??
• ? ? ?, ? ? Z
• behavioral model G
• composition constraints
• Example

FB C
Cap. array Switch
OTA
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Analog Platforms Design Flow

• Successive refinement/abstraction steps
• Bottom-Up phase define an abstraction ?l that
  maps l into l1
• ?l has to be conservative
• proceed tolower levelswithout iterations
• Simulation based performance generation can be
  conservative

level l1
level l
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Analog Platforms Design Flow

• Successive refinement/abstraction process
• Top-down phase optimization problem
• cost function C(ytop)
• application constraints
• platform constraints
• C(ytop) has to be minimizedin
• Result
• then, propagate down the stack

?
mapping space
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Performance Models

• Analog Platforms need a general and accurate
  scheme to represent performance models
• exploit a sampling scheme to approximate
  Image(fy())
• use a classifier to generate

IIP3
Y
Gain
K
Ibias
W
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Performance Models

• The approach applies at all platform levels
• only requires of platform instances F() and fy()
• Support Vector Machine classifiers DAC03
• hyperplane classifiers in Hilbert spaces
• is a Gaussian RBF kernel
• ? is the kernel parameter
• ?i are a set of weights
• xi, yi are variable and function values
• ? is a bias term
• heuristics to determine samples and ?
• false positives vs. false negatives

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Refining the Configuration Space

• Sampling is exponentially dependent on the size
  of K
• At platform levelsgt0 we have
• is constrained by
• At level 0, configuration spaces consist of
  physical parameters
• ? Ibias, Vbias, W1, L1, ? K
• Circuit functionality limits K through
• topological constraints
• physical constraints
• performance constraints
• Constraints effectively define

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Configuration Constraints

• Constraints can be represented as
• implicitly define
• Constraint relaxation
• f() cannot be expressed exactly
• analytical approximations to device behavior
• relax equalities to avoid configuration biasing
• e has to be estimated bounding analytical
  expression errors
• Configuration sampler in
• generate random solution to constraint system

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Analog Constraint Graphs

• Exploit bipartite graph representation Donald
• An ACG is an undirected bipartite graph (?, ?,
  ?), where
• ? ? ? are the design variables
• ? ? ? are equations on design variables ?
• ACGs represent under-constrained systems of
  equations with a set of inequalities
• A scheduling operation can be defined to provide
  efficient executable samplers in

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Case Study Pipeline ADC
-
-
-
ADC
ADC
DAC
ADC
DAC
ADC
DAC
Digital Correction Logic

• 80 MS/s, 14 bit pipelined ADC, digitally
  calibrated, 0.13 ?m CMOS, STMicroelectronics
• Focus on first pipeline stage
• assume following stages ideal
• Mixed signal case study
• first stage residue amplifier
• digital correction logic

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Level 1 Analog Platform

• Generate a Continuous Time Platform
• K is the set of MOS sizings and Ibias
• YVout(t), gain, HD3, noise, SR, f-3dB, Power
• F is is a Continuous Time behavioral model
• L requires Cload to be 32pF
• Constraints on K ISCAS05
• based on approximate IDS, gm equations
• relaxed constraint formulation
• constraints on bias current, output range,
  stability,

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Level 1 Analog Platform

• Folded Cascode topology
• defined similarly to telescopic
• same behavioral model
• Performance Model Generation
• exploit custom developed tools
• Client approximation process (Windows)
• Server simulation process (Linux)

Parameter K Y Num. Sim. Time
Telescopic R16 R6 2,134 9h
Folded Cascode R17 R6 2,838 12h
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Characterization Results
Performance Ranges
Parameter Telescopic Folded Casc.
Gain 26 ? 920 490 ? 3100
Bandwidth (MHz) 1.5 ? 8.9 0.29 ? 2.7
RMS noise (mV) 1.4 ? 6.2 2.8 ? 29
Power (mW) 38 ? 170 56 ? 180
Slew Rate (V/ms) 400 ? 2,400 840 ? 3,800

• Complex tradeoff
• gain
• bandwidth
• noise
• Model Accuracy
• 4 maximum relative error of AP models WRT Spectre

3D Y Space projections
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Level 1 Analog Platform

• Switch component
• fixed sizing
• K contains one point
• determined by ADC speed and noise requirements
• Behavioral model
• charge injection
• noise
• linearity
• Accurate simulation data

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Level 1 Analog Platform

• Platform instance provides a Discrete Time (DT)
  model for the first pipeline stage

• OTA model spans performance space of 2 topologies
• good accuracy
• maximum error WRT Spectre 5

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Level 1 Digital Platform

• Digital post-process Murmann03
• adjust gain
• linearize system
• Transfer Characteristic Estimation
• y a1xa3x3
• Characterization as a component
• bounds on accuracy of â1 and â3
• simulate the algorithm (a1, a3) ? (â1, â3)
• P(P, a1, a3 , â1, â3)1
• Polynomial Inversion
• compute
• predictor/corrector implementation scheme
• performance model for accuracy P(P, â1,
  â3)1

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Level 1 Digital Platform

• Platform library for digital enhancement
• simulation based characterization
• performance model
• P(P, a1, a3)1

Same flow for Analog and Digital Platforms
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Level 2 Mixed Signal Platform
ADC
-
ADC
ADC
GDEC
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System Optimization

• Top-down optimization problem
• minimize power consumption given
• linearity requirements
• minimum SNR
• Exploit simulated annealing
• stochastic global optimizer
• efficient behavioral and performance models

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Results

• Optimization performed in 18h
• based on simulation of ADC performance
• Results

Performance Optimal (Telescopic) Mapped Folded Cascode Reference
DNL (LSB) 0.4 0.6 0.44 0.68
INL (LSB) 0.1 0.21 0.15 0.26
SNR (dB) 86.3 86.4 84.3 84.3
PowerSHA (mW) 52.5 52.6 102 146
PowerOTA (mW) 47.7 47.9 97 146
AV0 220 214 1,186 1,492
Bandwidth (MHz) 3.3 3.3 0.79 1.35
Vnoise (mV rms) 2.5 2.61 7.9 8.86
G 7.3 7.27 7.8 7.94
PowerGDEC 4.8 4.8 4.2 -
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Conclusions

• A mixed signal design exploration methodology has
  been presented
• Analog platforms have been formally defined
• Simulation based performance models have been
  exploited
• conservative approximations of feasible spaces
• approximated with SVMs
• A challenging ADC design has been presented
• analog and digital platforms
• the mixed signal design exploration has been
  solved with SA
• Results demonstrate the effectiveness of the
  approach
• automatic topology selection
• power reduced by 64 WRT reference design

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Thanks.