Seamless CVE Nader Michou March 29 2005

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Seamless CVENader MichouMarch 29 2005
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Traditional Design

• High Level system Design
• partition the design into major
  subsystems
• Detailed Design And Implementation
• Hardware and software follow separate paths
• Physical Integration
• load the software onto the hardware and
  test

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Seamless CVE Design
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Accelerated Co-verification

• useful amounts of software can be run on
  simulated hardware.
• Separate the processors function from its
• interface
• Allow selective suppression of bus cycles
• in the logic simulation

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Seamless Components

• Software Simulator
• The software simulator executes machine code
  that you produce when you cross-assemble or
  compile your target software for the specific
  processor.
• Co-verification Kernel
• controls communications between the
  software
• and logic co-verification.
• Logic simulator and logic simulation kernel
• The Logic Simulator controls execution of
  the design. Then the
• Logic Simulation Kernel executes the
  HDL co-verification of the
• design.

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Seamless Components
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Software Co-verification

• Seamless comes with an instruction set model
  (ISM) and
• a bus-interface model (BIM).
• By running the Instruction Set Model (ISM) on a
  software simulator, software co-verification-
  sometimes referred to as Instruction Set
  Simulation (ISS) - can be performed much more
  quickly than logic co-verification because it
  does not have to calculate all the signal
  transitions that occur in the gates and registers
  within the processor.
• To perform software co-verification,
• generate machine code for the target
  processor.
• you are free to use any high-level language,
  assembly language, or mixture of the two that the
  cross-development tools support.

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Software Co-verification

• When the software is ready to be tested with the
  hardware design, you introduce the Seamless
  application into the design flow.
• The ISM provided with any given PSP is developed
  using a targeted software simulator, such as the
  XRAY Debugger, which is part of an integrated
  development and testing environment. Therefore,
  the Processor Support Package determines both the
  simulator required to perform co-verification and
  the level of software simulation that occurs
  during co-verification.

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Host Code Execution

• With Host Code Execution (HCE), you can use the
  native compilers on your workstation to develop
  embedded software. Instead of using a software
  simulator,
• One advantage to using Host Code Execution is
  that it is much faster than executing machine
  code on a software simulator.
• Another advantage is that it allows you to
  implement portions of the software for an
  embedded system in a high-level language and test
  the software directly with the logic
  co-verification, without having machine code
  available.
• You use the HCE Application Program Interface
  (API) to link embedded software to the logic
  co-verification process. This API exports a set
  of data-access functions connecting the compiled
  code to the bus-interface model in the logic
  simulator.

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Bus-Interface Models

• the bus-interface model supplies the input and
  output pin behavior.
• You instantiate the bus-interface model in a
  design and run the design on a logic simulator,
  such as ModelSim.
• The bus-interface model performs only pin
  transitions, and does not model the internal
  logic of the processor, so co-verification is
  much faster than with a complete functional
• model.

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Bus-Interface Models
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Optimizable Memory Models

• The main difference between optimizable memory
  models and conventional models is that in
  optimizable models, the memory contents exist in
  a memory array maintained by the Coherent Memory
  Server.
• Both the software simulation and the logic
  simulation can access the memory independently.
• Seamless application suppresses activity in the
  logic simulation in order to accelerate
  co-verification.

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Seamless Memory Architecture
Software Process
Hardware Process
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Categories Of Optimizable Memory

• Generic Optimizable Memory Models
• which are supplied with Seamless. A
  dynamic RAM, a static RAM, a dual port RAM, a
  FIFO, and a register element.
• Denali Memory Models
• which you create with the Pure View
  application from Denali Software, Inc.
• With Pure View, you are able to model
  more complex memory devices than the generic
  models available with Seamless.
• Models that use the Seamless HDL Memory Interface
• which allows you to convert existing
  models to optimizable models.
• Memory within C-Bridge Models

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C-Bridge Models

• The C-Bridge API is an interface that allows
  hardware design models expressed in high-level
  languages to participate in co-verification with
  Seamless.
• The C-Bridge API accepts hardware design models
  written in System C, C, or C. For the purposes
  of Seamless documentation, hardware design models
  that are written in System C, C or C and that
  use C-Bridge are referred to as C-Bridge models.

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Optimizations

• Trading simulation detail for speed to
  obtain the right mix
• of accuracy and performance.
• Data Access Optimization
• Instruction Fetch Optimization
• Time Optimization

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Full Simulation Optimized
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Data Access Optimization

• Data Access Optimization
• allows you to disable hardware bus cycles
  when
• accessing optimizable memory addresses or
• address ranges.
• The logic simulation continues to advance,
  but it
• does so without bus activity during
  optimized
• memory accesses.
• The purpose of Data Access optimization is
  to
• accelerate co-verification by suppressing
  bus
• activity in the logic simulation during
  memory
• accesses.

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Data Access Optimization
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Instruction Fetch Optimization

• Instruction Fetch Optimizationis a convenient
  way to eliminate bus activity for all instruction
  fetches from optimizable memory.
• Instruction Fetch Optimization is a convenient
  way to eliminate a class of bus cycles that
  rarely affects co-verification accuracy.

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Instruction Fetch Optimization
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Time Optimization

• Time Optimization
• allows you to decouple the time
  synchronization between hardware
• and software co-verification and run the
  software simulation at full
• speed most of the time.
• The software process runs without
  advancing the logic simulation
• until either an access to a
  non-optimized address range occurs or a
• specified number of software cycles
  occurs.
• Off
• (Run Logic Simulator for every software
  cycle.)
• Full
• (Run Logic Simulator only for
  non-optimized memory accesses.)
• Ratio
• (Run Logic Simulator for at least __
  cycles every __ software cycles.)
• Ratio Time optimization is useful in an
  interrupt-driven system,

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Time Optimization
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Memory Mapping

• Memory mapping defines the way in which software
  access to memory correlates with the logic
  simulation.
• The Seamless application requires two kinds
  of memory mapping
• Memory Instance mapping
• Specifies how Seamless memory instances
  map into the
• address space of a given processor.
• Memory Access mapping
• Defines how different ranges of memory may
  be
• accessed.

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Memory Mapping

• You can set the access type of any non-
• optimizable memory address range to
• Hardware-only, Software-only, or
• Illegal. Initially, all non-optimizable
• ranges are set to Hardware-only access.

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Memory Access Types

• Software
• Hardware
• Optimizable
• Illegal

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Seamless Coherent Timers

• When operating in time-optimized mode, the
  Seamless application decouples the software
  simulator from the much slower logic simulation.
  This allows the software simulator to run at full
  speed.
• The Seamless Coherent Timer Interface allows you
  to seamlessize existing timer models so they
  can maintain an accurate count of clock cycles
  when the Seamless application is running in
  time-optimization mode.

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HW 8 Steps Briefly

• Setup logic simulator
• Setup software simulator
• Map memory instances
• Set memory ranges
• Run
• No Optimization
• Address Range optimization
• Time Optimization
• Instruction Fetch Optimization

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Thank you