Timing Recovery Unit for a 1'6 Mbps DSSS Receiver

1
Timing Recovery Unit for a 1.6 Mbps DSSS Receiver

• EE225C Final Project Presentation
• M. Josie Ammer (mjammer_at_eecs.berkeley.edu)
• Mike Sheets (msheets_at_eecs.berkeley.edu)
• 12 December 2000

2
Outline

• Introduction Problem Statement
• Existing Solutions
• Project Overview
• Overall System Block Diagram
• Sub-system Block Diagrams
• Coarse Timing Block
• Fine Timing and Carrier Offset Estimation Block
• CORDIC Block
• PLL Block
• System Controller Block
• Chip Floorplan
• Simulation
• Analysis Conclusion

3
Introduction

• Trend toward mostly digital transceiver
• Digital circuitry improves with scaling
• Analog gets worse (voltage reduction)
• More components gt digital back-end
• Low power digital techniques
• Critical for low power transceiver design
• Voltage scaling, arithmetic techniques, etc.

4
Problem Statement

• Design a 1.6 Mbps DSSS timing recovery unit
• Modulation
• Length 31 PN code
• QPSK symbol constellation
• System specifications
• Maximum frequency offset of /- 200 KHz
• Minimum input SNR of 1 dB
• Input is in-phase quadrature samples at 200 MHz
  with 7 bits each
• Primary design criterion is power minimization

5
Existing Solutions

• Synchronization algorithm classes
• Class DD/DA Decision Directed or Data Aided
• Class NDA Non-Data Aided
• Estimation method
• Feedforward
• Feedback

6
System Block Diagram
7
Coarse Timing Block
Expected match filter magnitude squared output
Coarse Timing Block Diagram
8
Coarse Timing Datapath
sfrac(7) _at_ 25MHzI and Q
sfrac(12) _at_25MHzI and Q
ufrac(24)_at_25MHz
Pilot MF
2
INDEX
MAX
sel1..0
Stream 2,4,7
VALUE
gt
Pilot MF
2
S
lt
Pilot MF
2
low_thresh
T_HI
T_LOW
Abs. Val. S
2
x1.75

TimeAvg.
2
Abs. Val. S
gtgt3
RSSI23..0
x1.09375
2
Abs. Val. S
sfrac(7) _at_ 25MHzI and Q
sfrac(12) _at_ 806kHzI and Q
ufrac(24) _at_ 806kHz
9
CT Explored Architectures
31-tap, pilot match FIR filter (transposed form)
Xin

addsub
addsub
addsub
addsub
z-1
z-1
z-1
0
spread
29
30
31
0
Architecture 0
Architecture 1
Architecture 2

• Six 31-tap, pilot match FIR filters account for
  70 of total design area
• Architecture 2 is estimated by MC to be better in
  terms of power
• Carry-save format uses more area, but in some
  cases reports lower power consumption
• Final adder type is carry look-ahead (12 bit
  operands)

10
Fine Timing Block Diagram
Stream with maximum likelihood timing
Frequency offset lt 200 KHz
Frequency estimate within 2.5 KHz

• Estimate frequency offset within 2.5 KHz
  (3-sigma)
• Choose stream with maximum likelihood timing
• Maximum likelihood frequency estimation operating
  with known timing and data (algorithm Meyr, et.
  al.)
• Goal Lowest power implementation that meets
  timing specs

11
FT Explored Architectures

• 6 bits in, 16 bits out
• Arch. 2
• CLA final adders
• 12 bits in, 28 bits out
• Arch 3
• Carry save arith.
• CLA final adders
• Problem Large area
• Arch 1 second lowest power, reduced area

Architecture 1
Architecture 2
Architecture 3
Architecture 4
12
CORDIC
CORDIC slice
CORDIC stage0 slice

• Slice implemented in Module Compiler
• Instantiated 29 times
• Structure
• Full
• Pipelined
• High speed
• Recursive
• Shared slice
• Significantly less area
• Used 3 times
• Rectangular to Polar conversion (x1)
• Angle rotation (x2)

Recursive CORDIC structure
13
PLL Block Diagram
14
System Controller Block Diagram

• Timing and synchronization
• Controls gated clocks to the other blocks
• Counts the chip offset into a symbol
• Mode controller
• Idle, Carrier Search, Acquisition, Data Reception

15
Chip Floorplan
16
Simulation Strategy

• Simulate each block separately using separate
  test benches
• Match datapath blocks to Module Compiler
• Simulate state machines within Simulink/StateFlow
  (SF2VHD later)
• Create a transmitter and channel model for system
  testbench
• Only needs to send pilot symbols (1i) using
  pilot PN code
• Send a train of at least 35 pilots
• Verify the correct sequence and operation of the
  blocks

17
Coarse Timing Datapath Simulation
Possible pilot matches
Blocks verified separately in Simulink
VHDL and Simulink outputs match exactly
18
Frequency Estimation Simulation
50e3 rotation introduced
0.3950e3/800e32pi freq offset estimate
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Transmitter Channel Models
Transmitter chain
Channel model
200 KHz rotating phasor
SNR 1dB
20
Pilot Search Mode
Correlation peak
Adaptive thresholds
Pilot detected indication after third correlation
peak
Symbol strobe signal in third chip of pilot
symbols
21
Acquisition Mode Freq. Est.
Garbage wont exist in final implementation
because the clock will be gated
Fine Timing Carrier Offset Estimation
Output of Rotate Correlate with residual offset
less than 2.5 KHz
22
Acquisition Mode PLL Training
Phase error
Phase correction
23
Analysis Discussion

• Future Work
• PLL fixed-point design refinement
• Augment the hardware to support data mode
• Translate the state machines using SF2VHD
• Harden blocks
• Incorporate transmitter onto chip
• Alternative solutions
• AGC prior to ADC
• Interpolator instead of parallel streams

24
Conclusion/Summary

• Nominal clock rate is 25 MHz
• Estimated power consumption
• Carrier search mode 7.6 mW
• Acquisition mode 0.47 mW
• Data reception 1 mW
• Estimated die area is 2.2 mm2