Computer Architecture Lecture 3

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Computer ArchitectureLecture 3 Part 111th
May, 2006

• Abhinav Agarwal
• Veeramani V.

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Quick recap Pipelining
source http//cse.stanford.edu/class/sophomore-co
llege/projects-00/risc/pipelining/
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Quick recap Problems

• Data hazards
• Dependent Instructions
• add r1, r2, r3
• store r1, 0(r4)
• Control Hazards
• Branches resolution
• bnz r1, label
• add r1, r2, r3
• label sub r1, r2, r3
• Structural Hazards

IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
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Data Hazards

• RAW hazard Read after Write
• add r1, r2, r3
• store r1, 0(r4)
• WAW hazard Write after Write
• div r1, r3, r4
• add r1, r10, r5
• WAR hazard Write after Read
• Generally not relevant in simple pipelines

IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
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Remedies

• Bypass values (Data forwarding)
• RAW hazards are tackled this way
• Not all RAW hazards can be solved by forwarding.
  E.g. Load delay, What about divide?
• What is the solution?
• Static compiler techniques

IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
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Can we do better?

• Execute independent executions out-of-order? What
  do we require for this?
• lw r4, 0(r6) Cache miss - Takes time
• addi r5, r4, 0x20
• and r10, r5, r19
• xor r26, r2, r7
• sub r20, r26, r2
• Fetch more instructions...
• Instructions should be commited in-order
• Memory instructions? Is dependency clear?

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The WAW hazard

• Is it unavoidable? What is the reason for such
  hazard?
• Register renaming
• More physical registers
• Logical registers mapped to physical registers
  available when the instruction is decoded

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References

• http//en.wikipedia.org/wiki/Hazard_(computer_arch
  itecture)
• http//www.csee.umbc.edu/plusquel/611/slides/chap
  3_3.html