5. Combinational Circuits

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5. Combinational Circuits

• Objectives To recognize the principal types of
  combinational circuits
• Adders and subtracters
• Decoders, comparators, converters
• Multiplexers and demultiplexers
• Logical programmable ROM, PAL, PLA
• Arithmetic logic unit (ALU)
• Various combinations for their analysis and
  synthesis, and the synthesis of functions in
  general.

2
5.1 Adders and Subtracters

• Already discussed the adder (Chap. 2)
• Subtracters
• Half-subtracters, elementary
• Adders/subtracters
• Subtracters with several bits

I
D
B
A
E
3
5.2 Decoders

• Decode a binary word.
• It has n inputs and m 2n outputs.
• A B D0 D1 D2 D3
• 0 0 1 0 0 0
• 0 1 0 1 0 0
• 1 0 0 0 1 0
• 1 1 0 0 0 1

0
D0
21
A
1
D1
Decoder 2 to 4
2
D2
20
B
3
D3
4
Synthesis with decoders

• Any binary function f(x1, x2, ..., xn) can be
  realized simply by a n x 2n decoder and an OR
  gate.
• Example Elementary adder
• Decoder with Enable (E) input
• E allows enable/disable a decoder.
• If E 0, all the outputs are to 0.
• Useful in the synthesis of large decoders

5
Synthesis with decoders

• Elementary adder
• S (X, Y, Z) Sm (1, 2, 4, 7)
• C (X, Y, Z) Sm (3, 5, 6, 7)

6
Synthesis of large decoders

• 4 x 16 decoder using two 3 x 8 decoders

7
Synthesis of large decoders

• 4 x 16 decoder using 2 x 4 decoders

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5.3 Magnitude Comparators

• Carry out the comparison of two binary numbers.
• The comparator of binary numbers (A and B) of
  four bits to indicate if AgtB, AltB or AB. It has
  moreover three entries (AgtB, AltB and AB)
  allowing the sequence of the circuits to compare
  numbers of more than four bits (in cascade).

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5.4 Code Converter

• Achieves the conversion of information in one
  form of binary representation to another form of
  binary representation.
• Examples
• 1CF to 2CF
• BCD to Excess-3
• BCD to representation in 7 segments
• As in a display
• Various options (0 to 9, 0 to 9 with values
  indifferent for entries 10 to 15, 0 with F, etc.)

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5.5 Multiplexers

• Use

Multiplexing
Demultiplexing
Source 0
Source 1
. . .
. . .
Un seul lien
Source 2n-1
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Multiplexers

• Multiplexer (MUX) selects one out of 2n inputs of
  information and directs it to the output.
• Example 4-to-1 Multiplexer.
• S1 S0 Y
• 0 0 D0
• 0 1 D1
• 1 0 D2
• 1 1 D3

0
D0
1
D1
MUX 4-to-1
S
Y
2
D2
3
D3
21
20
S1
S0
12
Synthesis with multiplexer

• That is to say a binary function f(x1, x2, xn),
  its realization with a multiplexer is done
  according to the following procedure
• 1. Develop the Truth Table of f.
• 2. If the multiplexer is rather large
• (2n to 1 MUX)
• Then not of problem. All is direct!
• If not use 2n-1 to 1 MUX.

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Synthesis with too small MUX

• Example f(A,B,C) åm (2, 3, 5, 6)

4-to-1 MUX
C
f
B
A
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Synthesis with too small MUX

• Example f(A,B,C) åm (2, 3, 5, 6)

4-to-1 MUX
f
B
A
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Synthesis with too small MUX

• f(A,B,C,D) åm (0, 4, 5, 9, 13, 14, 15)
• 3 solutions, according to what is required

CD
C
CD
CD
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Complex Multiplexers

• It is possible to design multiplexers much more
  complex for particular uses
• Multiplexers of more than one bits
• Multiple multiplexers
• Multiplexers designed using smaller multiplexers
  (economy?)

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Demultiplexers

• It distributes the bit E (or the word) to one of
  the 2n possible destinations (specified by S).

0
D0
1
D1
DEMUX 1 to 4
E
E
2
D2
3
D3
21
20
S1
S0
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5.6 Three technologies of programmable logic
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ROM (Read-Only Memory)

• Circuit made up of a matrix of register-memory
  for storing a fixed length information
  permanently.

ROM
(adresses)
(data)
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Synthesis with ROM

• Any set of boolean functions f1(x1, x2, xk)
  fn(x1, x2, xk) can be implemented using
  (2k n) ROM and one level of programming.
• Examplef1(I1, I0) Sm (1, 2, 3),f2(I1, I0)
  Sm (0, 2),4x2 ROM

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Synthesis with ROM

• Alternative representation of the solution
• fuse intact
• f1(I1, I0) Sm (0, 3)
• f2(I1, I0) (I1 I0)'
• f3(I1, I0) PM (1)
• The OR gates have all 4 entries nevertheless!

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5.7 PLA(Programmable Logic Arrays)

• Programmable logic arrays are made of
• One layer of product terms (AND gates)
• One layer of sum terms (OR gates)
• Three layers with inverter/fuses
• Fuses in each layer are programmed

m fuses
ninverters
n x k fuses
k product terms (AND gates)
m sum terms (OR gates)
k x m fuses
moutputs
minverters
n x k fuses
ninputs
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Synthesis with PLA

• Example
• F1(A,B,C) Sm(3, 5, 6, 7)
• F2(A,B,C) Sm(0, 2, 4)
• Which are the terms produced of F1 , F2 , F1 and
  F2 ?

F1(A,B,C) AB AC BC F1 F2 5 terms F1
(A,B,C) AB AC BC F1 F2 4
terms F2 (A,B,C) AC BC F1 F2 3
terms F2 (A,B,C) AB C F1 F2 5 terms
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Synthesis with PLA

• Example
• F1(A,B,C) Sm(3, 5, 6, 7) (AB AC BC)
• F2(A,B,C) Sm(0, 2, 4) AC BC
• The product terms are AB, AC and BC
• Programming

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Synthesis with PLA

• Example
• F1(A,B,C) Sm(3, 5, 6, 7) (AB AC BC)
• F2(A,B,C) Sm(0, 2, 4) AC BC
• The product terms are AB, AC and BC
• Programming

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Synthesis with PLA
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5.8 PAL(Programmable Array Logic)

• Programmable logic networks made of
• One layer of product terms (AND gates)
• One layer of sum terms (OR gates)
• Programmable fuses with the 1st layer
• More simplistic than the PLA, but less flexible

ninverters
n x k fuses
k product terms (AND gates)
m SUM terms (OR gates)
moutputs
n x k fuses
ninputs
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5.9 ALU (Arithmetic and Logic Unit)
A
B
Control
DEMUX
State (Status)
F
A
B
A
B
C
C
ALU
S
S
G
G
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Shift/Rotation and Status Bits

• Shift/rotation of a word of several bits via ALU.
• Status bits updated by ALU
• C Carry
• V Overflow Indicator
• Z Zero
• N Negative value
• Example
• Z (F0 Ú F1 Ú ... Ú Fn-1)

A
B
Logic of the conditions
S
F
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Complementary readings

• In Mano and Kime
• Sections 3.1 to 3.5
• Combinational circuits, except Logic Simulation
  (3.3)
• Section 3.7
• Multiplexers
• Sections 6.6 to 6.9
• Programmable logic, ROM, PLA, PAL
• Sections 7.7 to 7.8
• Arithmetic logic unit, shifter