Design Tools for SingleChip Networked Embedded Systems

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Design Tools for Single-Chip Networked Embedded
Systems

• A joint project between UCLA and UCI

Mani SrivastavaUCLA - Electrical
Engineeringmbs_at_janet.ucla.edu
Rajesh GuptaUCI - Computer Sciencegupta_at_uci.edu
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UCI Research Organization Focus

• Embedded and Adaptive Computing Systems
• Group divided into two focus sub-groups

• Design Automation
• Focus on system design tools
• HDL design optimizations
• Timing analysis, simulation
• Interconnect-dominated data-path circuit design
• Integrated Embedded Systems Automation Group
  (iESAG)
• 5 graduate students
• http//www.ics.uci.edu/iesag

• System Design
• Focus on system design
• From architectural design to circuit-level
  implementation
• Adaptive Memory Reconfiguration Management (AMRM)
  Group
• 8 graduate students, 1 postdoc
• http//www.ics.uci.edu/amrm

Problems, techniques
Tools, methods
jointly with A. Nicolau
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Embedded System Characteristics
Man-machine Interface
Instrumentation Interface
Embedded System
Controlled Object
Operator
The Environment

• Reactive interaction with the environment
• Operate under constraints
• functional, timing, performance (power, cost,
  size, reliability etc)
• Concurrent processing
• Increasingly implemented as microelectronic
  systems
• design process must consider aspects of VLSI
  design as well as traditional system design.

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Timing-Driven Design

• Consider timing constraints early
• Use time budgets
• across design stages
• within a design stage
• Why this works?
• The task structure and timing requirements imply
  or impose time budgets.
• Challenges
• timing details linked to functional details
• budgeting may help

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Timing-Driven Design Process

• Provide models for
• the task structure
• timing constraints
• Derive the time budgets from timing requirements
• Validate the timing requirements
• Debug any timing violations
• Advantages
• provide time budgets early in the design flow to
  drive it
• reduce validation complexity from system level to
  task level
• analyze and validate design tradeoffs
• eliminate unnecessary guess and checks
• provide high-level simulation or prototyping

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Modeling Problems

• Model the task structure and different task
  behaviors
• task interaction (dependency, enabling, tokens,
  etc.)
• acyclic and cyclic task structures
• AND causality and OR causality
• Skipped and unskipped behaviors
• Model the timing constraints (using intervals)
• rate and separation
• given and required
• external and internal
• worst-case and average (over an interval, not
  probabilistic)

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Timing Problems

• Derivation (of internal timing constraints or
  time budgets)
• acyclic rate
• acyclic separation
• cyclic rate
• (cyclic separation is not studied.)
• Validation (of timing requirements)
• system level or task level
• combine acyclic and cyclic derivations
• Debugging (of timing violations)

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RADHA-RATAN

• Problems addressed
• Validation of end-to-end timing constraints
• Derivation of intermediate timing constraints
• Validation of intermediate timing constraints
• Solution Rate-based static timing analysis on
  GTG
• Rate derivation and validation using RADHA
• Derive individual task rates from input task
  rates
• Derive other intermediate constraints from task
  rates
• Validate end-to-end timing constraints using
  intermediate constraints
• Rate analysis using RATAN
• Validate intermediate constraints for cyclic
  portions

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1 Task Structuring

• Task structuring determines systems task and
  communication between them
• Based on GTG task graph model
• tasks and task interactions (enable, disable,
  trigger)
• additional design constraints mutual exclusion,
  priority
• Task structuring criteria
• data versus control flow
• GTG iteratively refined using RADHA-RATAN
• early exposition of design decisions related to
  pipelining, parallel execution etc.

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2 Process Timing Simulation

• Given
• task level time budgets (or internal timing
  constraints)
• task input/output characteristics
• task graph
• Generate
• a process timing model
• simulate to determine system-level timing
  behavior
• Approach
• GTG semantics are used to automatically generate
  Verilog code

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RADHA-RATAN Status

• Implemented in 10,00 lines of C code
• Designs Explored
• Dashboard controller Balarin et al.97
• timing driven task structuring, timing-driven
  task partitioning
• automatic analysis completed in seconds.
• Mobile satellite receiver from INMARSAT
  Goddard98
• provable bounds on response time performance
• Directed low frequency analysis
• from ALFS subsection from LAMPS MKIII
  antiesubmarine helicopter Goddard98
• Our tool handles cyclic components better
  (theoretically) than Goddards.
• Audio/video multimedia application
  Chatterjee96
• Airline reservation query server application
  Chatterjee96
• Synthetic aperture radar application Goddard98
• timing performance determination-- improves bound
  on performance

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UCLAs Research Group

• Networked and Embedded Computing Systems
• Current projects
• Wireless multimedia nodes
• reconfigurable and low-power architectures
• adaptive and energy efficient protocols
• wireless network processor
• Gigabit wireless IPv6 router
• architecture, QoS algorithms and protocols
• Sensor networks, and sensor-based computing
• middleware, protocols
• New initiative with UCI design tools for
  single-chip networked embedded systems

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Single-chip Networked Embedded Systems

• Communication networking is becoming central to
  modern embedded systems
• on-chip application computing is perhaps
  secondary
• often off-loaded to network servers
• Zillions of transistors complete integration of
  all layers of a networked node on a single chip
• physical ? transceiver, modem
• link/MAC ? packet scheduling
• routing ? routing protocols, NAT
• transport ? TCP
• application ? adaptive buffering
• IC designers becoming networked system designers

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Example A Wireless Network Processor Chip

• How will we design these system-chips?

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Beyond Core-based Design IP Integration

• Networked systems are standards driven
• IETF, ITU, CEBUS, 802.11, Bluetooth, HomeRF etc.
• Core-based design help, but still need system
  optimization
• product differentiation, performance (speed,
  power)
• Diversity is the key to networked embedded
  systems
• trade-off and optimization across the diverse
  system layers and functions on the chip

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Processing of Bits inNetworked Systems

• Protocol communication functions are central to
  chip functionality
• not addition, multiplication etc.

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Example Networked System Optimization

• Problem How to achieve highthroughput in a
  wireless system?
• Can select a modem sub-system that packs more
  bits/Hz, but it will tolerate less noise and be
  less robust so that link throughput may not
  improve
• Can increase transmit power in RF subsystem to
  improve robustness but this increases energy
  cost, reduces network capacity, and requires more
  expensive analog circuits (power amps)

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Example Networked System Optimization (contd.)

• Can reduce bits/frame to tolerate higher bit
  error rates (BER) and provide more robustness,
  but this may increase overhead and queuing delays
• Can increase precision in digital modem to reduce
  noise, but this leads to wider on-chip busses and
  more power consumption
• How should one select the right sub-systemoption
  and assign right parameter values?

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Current Design Methodology for Networked Systems

• Network protocol stacks modeled and developed
  using network system simulators
• e.g. OPNET (commercial), NS (internet related
  protocols), Parsec (wireless) etc.
• extremely important to study performance of a
  node as part of a large network
• Mapped to implementation using lower-level tools
• protocol compiler, straight VHDL etc.
• No propagation of implementation details back to
  networked system simulation

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Big Picture of UCI/UCLA Research

• Design environment for single-chip networked
  embedded systems
• Simulation of multi-node networked systems
• Modeling and synthesis of selected network node
  with gradual refinement to h/w-s/w-analog
  implementation with in-network simulation
• Optimizations and trade-offs across-the-layers
• what-if scenarios impact of protocol stack
  implementation details on overall network level
  application performance
• performance (e.g. power) in specific scenarios

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Synopsys Project Focus Timing Optimization
across Layers

• The granularity of natural (behavioral) timing
  constraint is different in different layers
• physical bit
• link/MAC frame
• network IP packet, ATM cell
• transport UDP datagram, TCP segment
• application speech codec frame, image frame
• Protocols and channel conditions dictate the
  relationship among the timing constraints and
  performance at different interfaces
• User only cares about app-level performance

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Envisioned Approach

• Synthesizable multi-layer models of networked
  nodes (transport, network, link/MAC, physical)
• Simulation of the model as part of network
  simulations in NS or Parsec
• Analyze and propagate application-level
  constraints across the layers
• Synthesize to RTL or lower level
• Simulation of RTL model as part of network
  simulations
• Design driver

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Possible Design Driver 1Wireless-Wired Router
SNMP
HTTP
Transport Layer (TCP)
Network Layer (routing, NAT, firewall, QoS)
802.11 MAC
Ethernet
DSSS Modem
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Possible Design Driver 2Wireless Sensor
Network Node
SmartSensorNode
T1
Event
Internet
SmartSensorNode
Gateway
T2
SmartSensorNode
T3
SmartSensorNode
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Wireless Sensor Network Node (contd.)
Sensor Node Control Query Server
Beamformation
Fuse features with neighbors
Query/corroborate with neighbors
cooperative
Transport
Fuse multiple on-board sensors
Routing
autonomous
Process single sensor
Link/MAC
Continuous sample, HW filter, threshold compare
Radio Modem
Sensor Signal Processing Services
Networking Services
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Open Issues

• Selection and implementation of design driver
• when and where?
• Relationship and integration of UCI/UCLA project
  with Synopsys high-level design modeling effort
• Need input to fit together project deliverables
  within Synopsys flows incorporating --Scenic, El
  Greco, Protocol Compiler.