Title: H. Bischof, A.N. Belbachir (TUVIE)
1SPU High Level Software
- H. Bischof, A.N. Belbachir (TUVIE)
- F. Kerschbaum, R. Ottensamer, P. Reegen, C.
Reimers (UVIE)
2Data Compression/Reduction Scheme
Figure 1. Data Compression/Reduction Scheme
3ASW Requirements - SPU HLSW Data Flow
- Spectroscopy (400 detectors, 50 test channels, 18
empty channels per SPU Module) - 2000 kbits/s (4000 kbits/s for both SPUs)
- Photometry (512 detectors per sub-image)
- 5 sub-images (1700 kbits/s for both SPUs)
- 340 kbits for the LWL SPU
- 1360 kbits/s for the SWL SPU
- Telemetry rate
- 120 kbits/s are available for science data
- Transparent mode max. of 28 selected detectors
in Spectroscopy or
max. of 185 selected detectors in Photometry - Default mode Spectroscopy 97,14 kbits/s
Photometry 105,3 kbits/s
4ASW Requirements - Telemetry rates
Figure 2. Telemetry rates for the SWL and LWL SPU
5ASW Requirements - Default Mode in Spectroscopy
Figure 3. Default Compression Mode in Spectroscopy
6Data Compression/Reduction - Spectroscopy
7Data Compression/Reduction - Spectroscopy
8Data Compression/Reduction - Spectroscopy
- Evaluation of ramp fitting algorithms and test
results
9Data Compression/Reduction - Spectroscopy
Ramp 2
Ramp 3
10Data Compression/Reduction - Spectroscopy
- Analysis with simulated and real test data
- Status
- Preprocessing, glitch detection
- Ramp Fitting cumulative errors ? difference
scheme RANSAC (2 point with least square errors)
implemented - Integration mean algorithm implemented
- TRR SRR Reference value Difference values
11ASW Requirements - Default Mode in Photometry
Figure 4. Default Compression Mode in Photometry
12Data Compression/Reduction - Photometry
- Evaluation of averaging algorithms and test
results
13Data Compression/Reduction - Photometry
Voltage
Voltage
Plateau 1
Plateau 3
Time
Time
Voltage
Mean Median Sample Difference Real readout
Error Plateau 1 Plateau 2 Plateau 3
Mean 0,2 2,5 16,7
Median 0,0 0,3 0,0
Sample Difference 0,1 0,1 0,1
Plateau 2
Time
14Data Compression/Reduction - Photometry
- Analysis with simulated data from our data
generator - Status
- Preprocessing, glitch detection
- Robust Averaging mean algorithm implemented
(calibration on ground) - Integration mean algorithm implemented
- TRR SRR Reference value Difference values
15SPU HLSW Context Diagram
Figure 5. SPU HLSW Context Diagram
16SPU HLSW Concept
- HLSW consists of three main parts
- Communication Interfaces to DPU and to DEC/MEC
- Watch Process (Command Acknowledgement)
- Application Software (Reduction/Compression)
Figure 6. SPU HLSW Concept
17SPU SW Interfaces
- DPU TO SPU SW Interface
- Communication is bi-directional (commands,
response, HK and compressed data) - All SPU SW activities are commanded by DPU(e.g.
start, stop, ) - SPU SW acknowledges the reception of all DPU
commands according to the communication protocol - SPU SW sends telemetry packets to DPU
- DPU checks the life of the SPU SW via the HK
- DEC/MEC to SPU SW Interface
- Communication is unidirectional (DEC/MEC to SPU)
- Packet from DEC/MEC to SPU consists of science
data and a header - Science data are detector readouts and test
channels - Header contains the instrument configuration and
the compression parameters
18Memory Description
- 1.5MB EEPROM
- 32KB DPRAM
- 7MB RAM
- 1 Mbytes for program storage
- 0.25 Mbytes for SW tables storage
- 1 Mbytes for input science data buffering
- 0.25 Mbytes for the DEC/MEC header buffering
- 0.5 Mbytes for output data buffering
- 4 Mbytes are for processing, etc.
Figure 7. Memory Distribution for the SPU HLSW
19SPU HLSW Status
- SPU HLSW design frozen
- SPU HLSW Interfaces with DPU and DEC/MEC
- Interface Control Document are under
configuration control - Software interfaces have been verified under test
environment (PCemulator) - Detailed description of LLSW drivers are
available since 2001, 13 Dec. for the integration
on the real HW - Application Software
- Mechanism has been verified under test
environment (PCemulator) - Performance not tested (individual compression
modules tested Prelimi.) - No real data
- No representative development HW
20PA/QA Activities and Schedule
- PACS PA Plan is adopted (from IFSI)
- SPU Test Plan is under configuration control
- SPU HLSW Interface tested under test environment
(PC Emulator Spacewire Board) - SPU HLSW individual module complexity tested in
Sigma board - Schedule
- SPU SW Interfaces and application SW mechanism
have been tested - SPU HLSW functionality will be tested at IAC
(Spain) - Test at IAC is planned in March/April 2002
- Delivery of SPU HLSW to project by begin May
21Summary and Perspective
- SPU HLSW Interfaces tested with OBS Simulator
- Preliminary Application SW modules are ready for
integration and performance tests in real HW - Several ramp fitting and averaging algorithms are
tested - It is still possible to add new algorithms to
this library - New algorithms will be tested (functionality and
performance) - Verification of SPU HLSW functionality will be
done at IAC (Spain) in March/April 2002