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DIO2 Board

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when exec = -- execute instr without fetching next one ... ( addr data ) 'fetch' data from addr. WHYP words to read and write data to memory ... – PowerPoint PPT presentation

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Title: DIO2 Board


1
DIO2 Board
  • Projects

2
DIO2 Board
  • CPLD Interface
  • Seven-segment displays and LEDs
  • LCD Display
  • Pushbuttons and Switches

3
DIO2 circuit board block diagram
4
Top-level design for DIO2 interface
5
buff3.vhd
en
library IEEE use IEEE.STD_LOGIC_1164.all entity
buff3 is generic (widthpositive) port(
input in STD_LOGIC_vector(width-1 downto 0)
en in STD_LOGIC output out
STD_LOGIC_vector(width-1 downto 0) ) end
buff3 architecture buff3 of buff3 is begin
output lt input when en '1' else (others gt
'Z') end buff3
input
output
6
DIO2 CPLD VHDL Code
library IEEE use IEEE.STD_LOGIC_1164.ALL use
IEEE.STD_LOGIC_ARITH.ALL use IEEE.STD_LOGIC_UNSIG
NED.ALL entity d2io is Port ( btns in
std_logic_vector(14 downto 0) switchs
in std_logic_vector(7 downto 0)
leds out std_logic_vector(15 downto 0)
data inout std_logic_vector(7 downto 0)
addr in std_logic_vector(5 downto 0)
sseg out std_logic_vector(6 downto 0)
ssegdp out std_logic
ssegsel out std_logic_vector(3 downto 0)
cs in std_logic we in
std_logic oe in std_logic
clk256 in std_logic) end d2io
7
architecture rtl of d2io is signal data_out
std_logic_vector(7 downto 0) signal sseg_reg
std_logic_vector(15 downto 0) signal digit
std_logic_vector(3 downto 0) signal count
unsigned(1 downto 0) signal leds_i
std_logic_vector(15 downto 0) signal strobe
std_logic begin ssegdp lt '1' data lt
data_out when (oe '1' and cs '1') else
(others gt 'Z') data_out lt btns(7 downto 0)
when addr(1 downto 0) "00" else '0' btns(14
downto 8) when addr(1 downto 0) "01" else
switchs
8
strobe lt cs and we leds lt
not(leds_i) process(strobe) begin if(falling
_edge(strobe)) then case addr is when
"000100" gt leds_i(7 downto 0) lt
data when "000101" gt leds_i(15 downto
8) lt data when "000110" gt sseg_reg(15
downto 8) lt data when "000111"
gt sseg_reg(7 downto 0) lt data when
others gt NULL end case end if end
process
9
process(clk256) begin if(rising_edge(clk256))
then count lt count 1 end if end
process with count select digit lt
sseg_reg(7 downto 4) when "00", sseg_reg(3
downto 0) when "01", sseg_reg(15 downto 12)
when "10", sseg_reg(11 downto 8) when others
process(count) begin ssegsel lt (others gt
'0') ssegsel(conv_integer(count)) lt '1' end
process
10
with digit select sseg lt "1001111" when
"0001", --1 "0010010" when "0010", --2 "000011
0" when "0011", --3 "1001100" when
"0100", --4 "0100100" when "0101", --5 "010000
0" when "0110", --6 "0001111" when
"0111", --7 "0000000" when "1000", --8 "000010
0" when "1001", --9 "0001000" when
"1010", --A "1100000" when "1011", --b "011000
1" when "1100", --C "1000010" when
"1101", --d "0110000" when "1110", --E "011100
0" when "1111", --F "0000001" when
others --0 end rtl
11
DIO2 Board
  • CPLD Interface
  • Seven-segment displays and LEDs
  • LCD Display
  • Pushbuttons and Switches

12
Seven-segment LED display
13
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14
In opcodes.vhd
constant DIO2store opcode X"010F" --
DIO2! constant LCDistore
opcode X"0110" -- LCDinst!
constant LCDdstore opcode X"0111" --
LCDdata!
15
In wc16_control add.
signal ccycle STD_LOGIC_VECTOR (5 downto 0)
MultiCC process (clk, clr, current_state) begin
if clr '1' then ccycle lt "000001"
elsif (clk'event and clk '1') then if
current_state exec then ccycle lt ccycle
1 else ccycle lt "000001" end if
end if end process MultiCC
16
In wc16_control add.
when exec gt -- execute instr without fetching
next one if (icode X"010E" or icode
X"010F") and ccycle lt 3 then next_state
lt exec elsif (icode X"0110" or icode
X"0111") and ccycle lt 8 then next_state
lt exec --elsif icode
X"Code_for_multi-cycle" -- and ccycle lt
Num_cc_to_exec then -- next_state lt exec
else next_state lt fetch -- go to
fetch state end if
17
In wc16_control add.
DIO2! ( data addr .. )
when DIO2store gt cs lt '1' oe lt '0'
pinc lt '0' if ccycle 1 then we
lt '1' else tload lt '1' nload lt '1'
tsel lt "111" nsel lt "01"
dpop lt '1' end if
18
D2DIGstore.whp
\ Test of DIO2 DIG!     D2DIG! ( n --
) DUP 8 RSHIFT \ n nHI 7 DIO2! \
display nHI 6 DIO2! \ display
nLO     main ( -- ) BEGIN waitB4
S_at_ \ get HI byte DUP DIG! 8 LSHIFT
waitB4 S_at_ \ get LO byte OR DUP DIG!
D2DIG! AGAIN
19
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20
\ led16.whp HEX   1ms_Delay ( -- ) 30D1 FOR
NEXT   .5sec_Delay ( -- ) 1F4 FOR
1ms_Delay NEXT   D2DIG! ( n -- ) DUP 8
RSHIFT \ n nHI 7 DIO2! \ display nHI
6 DIO2! \ display nLO   D2LD! (
n -- ) DUP 8 RSHIFT \ n nHI 5 DIO2! \
display nHI 4 DIO2! \ display
nLO  
LED16.whp
21
LED16.whp (cont.)
MAIN ( -- ) BEGIN 8000 10 FOR
DUP D2LD! DUP D2DIG! .5sec_Delay 2/
NEXT 10 FOR U2/ DUP D2LD! DUP
D2DIG! .5sec_Delay NEXT DROP AGAIN

22
DIO2 Board
  • CPLD Interface
  • Seven-segment displays and LEDs
  • LCD Display
  • Pushbuttons and Switches

23
DIO2 circuit board block diagram
24
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25
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26
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27
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28
In wc16_control add.
LCDinst! ( data 0 .. )
when LCDistore gt LCD_RW lt '0' LCD_RS lt
'0' pinc lt '0' if ccycle lt 7 then
LCD_E lt '1' else tload lt '1' nload lt
'1' tsel lt "111" nsel lt "01"
dpop lt '1' end if
LCDdata! ( data 0 .. )
when LCDdstore gt LCD_RW lt '0' LCD_RS lt
'1' pinc lt '0' if ccycle lt 7 then
LCD_E lt '1' else tload lt '1' nload lt
'1' tsel lt "111" nsel lt "01"
dpop lt '1' end if
29
Lcd3.whp
\ LCD for Digilab DIO2 \ LCD3.WHP   HEX  
1ms_Delay ( -- ) 30D1 FOR NEXT   30ms.Delay
( -- ) 1E FOR 1ms_Delay NEXT   hex2asc
( n -- asc ) 0F AND \
mask upper nibble DUP 9 gt
\ if n gt 9 IF
37 \ add 37 ELSE
30 \ else add 30
THEN
30
Lcd3.whp
lcd.init ( -- ) 30ms.delay 3C
0 LCDinst! \ 2 x 40 display 1ms_Delay
0f 0 LCDinst! \ display
on 1ms_Delay 1 0 LCDinst! \
display clear 1ms_Delay 1ms_Delay
6 0 LCDinst! \ entry cursor shift
off 1ms_Delay
31
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32
Lcd3.whp
hexgtlcd ( hex -- ) HEX2ASC 0
LCDdata! 30ms.delay   u.lcd ( u --
) \display T on LCD DUP C RSHIFT hexgtlcd DU
P 8 RSHIFT hexgtlcd DUP 4 RSHIFT hexgtlcd he
xgtlcd
33
Lcd3.whp
MAIN ( -- ) lcd.init BEGIN
waitB4 S_at_ \ get high byte DUP DIG! DUP
hexgtlcd 8 LSHIFT waitB4 S_at_ \ get low
byte OR DUP DIG! DUP hexgtlcd waitB4 u.lcd
\ display on lcd AGAIN
34
DIO2 Board
  • CPLD Interface
  • Seven-segment displays and LEDs
  • LCD Display
  • Pushbuttons and Switches

35
Top-level design for DIO2 interface
data_io
36
From DIO2 CPLD
data_out lt btns(7 downto 0) when addr(1 downto
0) "00" else '0' btns(14 downto 8) when
addr(1 downto 0) "01" else switchs
In opcodes.vhd
constant DIO2fetch opcode X"003A" --
DIO2_at_
In wc16_control.vhd
when DIO2fetch gt -- read 8-bit DIO2-bus (E1)
tload lt '1' -- DIO2_at_ ( addr data )
tsel lt "100" cs lt '1' oe lt '1'
In Lab9.vhd
E1 lt ground data_io data lt data_io
37
SW2test.whp
\ Test of DIO2 switches   main ( --
) BEGIN 3 DIO2_at_ \ read switches 4
DIO2! \ display on LD(70) AGAIN
38
BTN2test.whp
\ Test of DIO2 buttons   D2DIG! ( n --
) DUP 8 RSHIFT \ n nHI 7 DIO2! \
display nHI 6 DIO2! \ display
nLO   D2LD! ( n -- ) DUP 8 RSHIFT \ n
nHI 5 DIO2! \ display nHI 4 DIO2!
\ display nLO   main ( -- ) BEGIN
1 DIO2_at_ \ btns(158) 8 LSHIFT 0
DIO2_at_ \ btns(70) OR DUP DIG!
DUP D2DIG! D2LD! AGAIN
39
BTN2test2.whp
\ Test of DIO2 buttons     get.BTN2 ( --
n ) 1 DIO2_at_ \ btns(158) 8
LSHIFT 0 DIO2_at_ \ btns(70) OR
  main2 ( -- ) BEGIN BEGIN \ wait to
lift finger get.BTN2 0 UNTIL
BEGIN \ wait to press button get.BTN2
UNTIL get.BTN2 \ get button DUP
DIG! DUP D2DIG! D2LD! AGAIN
40
DigScroll
41
Random Number Generator
42
RAM Module Coregen IP
43
WHYP words to read and write data to memory
! ( data addr -- ) \ store data at addr _at_ (
addr data ) \ fetch data from addr
44
! ( data addr -- ) \ store data at addr
when store gt tload lt '1' nload lt
'1' tsel lt "111" nsel lt "01"
dpop lt '1' if ccycle
"000001" then pinc lt '0' we lt
'1' end if
45
In wc16_control add.
Store (!)
when exec gt -- execute instr without fetching
next one if (icode X"010E" or icode
X"010F") and ccycle lt 3 then next_state
lt exec elsif (icode X"0110" or icode
X"0111") and ccycle lt 8 then next_state
lt exec --elsif icode
X"Code_for_multi-cycle" -- and ccycle lt
Num_cc_to_exec then -- next_state lt exec
else next_state lt fetch -- go to
fetch state end if
46
_at_ ( addr data ) \ fetch data from addr
when ramfetch gt -- read RAM in E1
tload lt '1' tsel lt "100"
47
Hex to Decimal
H2D ( h d )
  • Push each decimal digit into stack. \ d4 d3 d2
    d1
  • 4 LSHIFT and
  • \ (d4 10 (d3 10 (d2 10 d1 ) ) )

48
Hex to Decimal
H2D ( h - d ) \ convert hex to decimal 0 a
UM/MOD \ get push decimal digit 0 a UM/MOD
0 a UM/MOD \ d4 d3 d2 d1 4 LSHIFT \
put in the right place 4 LSHIFT 4 LSHIFT
\ (d4 10 (d3 10 (d2 10 d1
) ) )
49
Example 5678 dec 162Eh
HEX H2D ( h - d ) \ convert hex to decimal
\ 162E 0 a UM/MOD \ 8 237 0 a UM/MOD \
8 7 38 0 a UM/MOD \ 8 7 6 5 4 LSHIFT \ 8
7 56 4 LSHIFT \ 8 567 4 LSHIFT \ 5678
50
Decimal to Hex
D2H ( d h)
  • Push each digit into stack. \ d4 d3 d2 d1
  • Multiply, drop and
  • \ ( d4 a ( d3 a ( d2 a d1 ) ) )

51
Decimal to Hex
D2H ( d - h ) \ convert decimal to hex 0 10
UM/MOD \ push decimal digit to stack 0 10
UM/MOD 0 10 UM/MOD \ d4 d3 d2
d1 a UM drop \ multiply digit by a a UM
drop a UM drop \ ( d4 a ( d3 a (
d2 a d1 ) ) )
52
Example 5678 dec 162Eh
HEX D2H ( d - h ) \ convert decimal to
hex \ 5678 0 10 UM/MOD \ 8 567 0 10
UM/MOD \ 8 7 56 0 10 UM/MOD \ 8 7 6 5 a
UM drop \ 8 7 38 a UM drop \ 8 237 a
UM drop \ 162E
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