Analyzing%20Reconvergent%20Fanouts%20in%20Gate%20Delay%20Fault%20Simulation

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Analyzing Reconvergent Fanouts in Gate Delay
Fault Simulation
Hillary Grimes Vishwani D. Agrawal
Dept. of ECE, Auburn University Auburn, AL 36849
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Outline

• Problem Statement
• Reconvergent Fanout Analysis
• Ambiguity Lists
• Fault Detection
• Detection Threshold
• Detection Gap
• Results
• Conclusion

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Definitions

• Gate Delay Fault Model
• Assume that a delay fault is lumped at a single
  faulty gate
• Detection Threshold
• Minimum size delay fault that is guaranteed to be
  detected by the test
• Detection Gap
• Relates the detection threshold to the slack at
  the fault site

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Problem Statement

• When signals produced by a common fanout point
  reconverge, the inputs to the reconvergent gate
  are correlated
• Conventional simulation ignores this correlation
  when bounded gate delays are used
• Produces pessimistic results in both bounded
  delay simulation and gate delay fault simulation

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Bounded Delay Simulation
0
1 3
3 5
1,3
1,3
1,3
1,2
4 11
1,2
1,2
2 5
1
1
3,4
1,3
1,3
1,3
5 9
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Reconvergent Fanout Analysis
Fall occurs at time x
Hazard cannot occur
0
1 x 3
3 5
1,3
1,3
1,3
1,2
4 6 11
1,2
1,2
x1 5
1
1
3,4
1,3
1,3
1,3
Output rises at least 1 unit after x
5 9
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Ambiguity Lists

• Ambiguity Lists generated at fanout points
  contain
• originating fanout name
• ambiguity interval min and max delays from
  fanout to gate
• Ambiguity list propagation is similar to fault
  list propagation in concurrent fault simulation

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Ambiguity List Propagation

• Ambiguity lists at the inputs of a reconvergent
  gate help determine its output
• If signal correlations are such that no hazard
  can occur, the hazard is suppressed
• Otherwise, the ambiguity lists are propagated to
  the gates output, and ambiguity intervals are
  updated

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Ambiguity List Propagation

• Bounded Delay Simulation
• Ambiguity lists propagated through every gate
• Detection Threshold Evaluation
• Ambiguity Lists propagated through downcone of
  the fault site

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Detection Threshold
Ts 12
Det. Threshold 8
0
1 3
3 5
1,3
1,3
1,3
1,2
4 6 11
2 5
1,2
1,2
Corrected Det. Threshold 6
1
1
3,4
1,3
1,3
1,3
5 9
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Detection Gap for a Gate
p1 - longest delay path through gate
PI
Ts
PO
p1 delay
slack
t
gap
Gate
p2 delay
DT(p2)
p2

• Ideal gate delay test should activate longest
  path p1, detection threshold slack, gap 0
• A test that activates path p2, p2 lt p1, gap
  detection threshold slack
• Smaller the gap, better is the test

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Results

• ISCAS85 benchmark circuits simulated with 10,000
  random vectors
• Simple wireload model
• Bounded delays set to (3.5n 14), where n is
  the number of fanouts
• Program can accept any available gate delay data,
  which may be normally available from process
  technology characterization

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Results Fault-Free Simulation
Circuit Without Reconvergent Fanout Analysis Without Reconvergent Fanout Analysis With Reconvergent Fanout Analysis With Reconvergent Fanout Analysis
Circuit Largest EA Largest LS Largest EA Largest LS
c3540 96.0 204.0 121.6 196.8
C5315 76.8 204.0 91.2 194.4
C6288 158.4 576.0 236.8 504.0
C7552 91.2 204.0 104.0 201.6

• Using reconvergent fanout analysis generally
  results in larger EA and smaller LS values at
  outputs
• More apparent for circuits that contain a large
  number of reconvergent fanouts, such as in
  multiplier circuit c6288

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Results Fault Simulation

• Average detection gap and fault coverage of
  faults detected with gap 3.5 recorded
• For fault coverage, faults are counted as
  detected if they are detected
• Through the longest path through the gate
• Through a path which is shorter than longest path
  by only one gate delay

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Results Fault Simulation
Circuit Without Reconvergent Fanout Analysis Without Reconvergent Fanout Analysis With Reconvergent Fanout Analysis With Reconvergent Fanout Analysis
Circuit Average Detection Gap Faults Detected with Gap 3.5 Average Detection Gap Faults Detected with Gap 3.5
c432 110.4 7.35 108.9 7.08
c499 51.7 4.91 44.0 12.85
c880 16.4 48.41 12.9 48.86
c1355 50.8 4.80 42.2 13.62
c1908 55.2 21.70 47.1 25.10
c2670 41.8 31.25 36.0 36.54
c3540 50.4 32.60 44.0 33.19
c5315 21.7 55.72 6.1 57.31
c7552 39.4 13.43 22.5 22.83
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Conclusion

• When reconvergent fanout analysis is used, gate
  delay fault simulation results are less
  pessimistic
• During simulation, ambiguity lists can grow quite
  large
• Efficiency in list propagation needs to be
  improved
• This min-max delay simulator has found
  application in hazard-free delay test generation