CriticalPathAware XFilling for Effective IRDrop reduction in AtSpeed Scan Testing

1
Critical-Path-Aware X-Fillingfor Effective
IR-Drop reductionin At-Speed Scan Testing

• X. Wen, K. Miyase, T. Suzuki, S. Kajihara
• Kyushu Institute of Technology
• Yuji Ohsumi
• Dai Nippon Printing, Co., Ltd.
• K. K. Saluja
• University of Wisconsin Madison

2
Outline

• Introduction Background
• Previous Work
• Critical-Path-Aware X-Filling
• Experimental Results
• Conclusions

3
At-Speed Scan Testing

• Timing-related defect became critical
• Feature sizes shrink into the DSM scale.
• Circuit speeds grow into the GHz domain.
• Emerging Test-induced yield loss
• Excessive IR-drop
• Short cycle for capturing a test response

Launch Capture
Response Capture
Test Vector Load Completed
Test Vector Unload Started
SE
At-Speed
CLK
SL
S1
C2
C1
Launch Of Capture scheme
4
IR-drop-induced yield loss

• IR-drop may cause timing violations.
• Increase gate delay
• Test IR-drop is higher than Functional IR-drop
• High switching activity such as scan shift
• Test vectors ignore functional constraints.
• Test clocking is not allowed in functional
  operation.
• Test IR-drop may break the functional IR-drop
  margin to fail a functionally normal circuit.

Fail
Test
Circuit
Circuit
IR-drop
IR-drop-induced yield loss
Functionally normal
Test induces IR-drop
5
Shift IR-drop Capture IR-drop

• Shift IR-drop
• Increase of clock skews make a scan chain fail
• Combinational logic portion has no actual harm
• Capture IR-drop
• Delay increased by IR-drop severe impacts on
  response capture.

Launch Capture
Response Capture
SE
CLK
S1
C2
SL
C1
6
Outline

• Introduction Background
• Previous Work
• Critical-Path-Aware X-Filling
• Experimental Results
• Conclusions

7
Previous Work

• Circuit modification S. Gerstendoerfer, et al.,
  ITC1999, etc.
• Preferable for shift IR-drop reduction
• May affect capture operation (test clocking,
  circuit timing,ATPG complexity)
• Data manipulationS. Remersaro, et al.,
  ITC2006, etc
• Preferable for shift capture IR-drop reduction
• May not good achievement for both shift capture
• Preferred solution of Total IR-drop reduction
• Circuit modification (Shift IR-drop reduction)
• Date manipulation (Capture IR-drop reduction)

8
Capture IR-drop Reduction

• X-filling S. Remersaro, et al., ITC2006X.
  Wen, et al., ITC2005, ICCD2006
• Assign logic values to X bits so as to reduce
  switching activity
• Full compatibility with any ATPG flow
• No circuit / ATPG impact

Test Cube c
PIs
POs
ltf(v) POgt
X 0 X 0 X 1
ltv PIgt
Comb. Portion (Gates)
PPOs
PPIs
v
f(v)
f
Scan FFs
ltv PPIgt
ltf(v) PPOgt
Capture
9
Problem of Previous X-Filling Methods

• Previous methods can only lead to the reduction
  of overall switching activity
• Ignoring the important fact that capture
  malfunction mostly occurs

FFs
G1
G2
G3
FFe
Start
End
Test Cycle
10
Paradigm Change in X-Filling

• IR-drop-induced capture malfunction often occur
  on an active critical path

• Active Critical Path
• A transition occur at the start of a path
• The transition uniquely controls the signal
  value at the end of the path

previous
indirect
Whole Circuit
IR-Drop-Induced Malfunction
X-Filling
11
Outline

• Introduction Background
• Previous Work
• Critical-Path-Aware X-Filling
• Experimental Results
• Conclusions

12
Critical-Path-Aware X-Filling

• Basic concept of the proposed method
• Quantitatively identify critical area in the
  circuit withactive critical path information
• Focus on the capture IR-drop reduction in the
  identifiedcritical area

POs
PIs
PPIs
PPOs
Combinational Portion
13
General Flow of the Propose Method
v test cube with X-bits
Critical Gate Identification
Critical Weight Calculation for Each Critical
Gate under v
d ? Logic Value Selection
s ? d
Y
Any more X-bit?
N
v fully-specified test vector
14
Critical Capture Transition Metric

• Quantitatively identify critical area in the
  circuit
• Active Critical Path ? Active Probability
• Critical Gate ? Critical Weight

POs
PIs
Combinational Portion
Active Probability
PPIs
PPOs
Critical Weight
Critical Capture Transition CCT(v)
15
Active Probability Calculation
16
Active Probability Calculation(cont.)
Before-Launch Cycle
After-Launch Cycle
V
1
G1
G1
FF1
X
FF1
FF1
G2
G2
FF2
FF2
X
FF2
AP(p, v)
?
17
Critical Gate

• Distance from critical paths is no greater than
  the given radius.

G6
G2
G8
e
G4
Critical Path p
G7
s
G5
G3
G1
18
Critical Weight

• The closer G is to the path, the higher the
  impact of G on capture malfunction.

Critical Path p1
AP(p1, v)
Test Cube v
Critical Path p2
AP(p2, v)
Non-Critical Path
19
Critical Capture Transition Metric
Combinational Portion
Test Cube v
1 X 0 X X 1
POs
PIs
PPOs
PPIs
m
å
( CW ( Gi , v ) ? fi ? ti )
CCT ( v )


i
1
20
Logic Value Selection

• Trial Calculation

Test Cube v
POs
1 X 0 X X 1
PIs
PPOs
PPIs
Select 1 as the X-filling Value
21
Outline

• Introduction Background
• Previous Work
• Critical-Path-Aware X-Filling
• Experimental Results
• Conclusions

22
Experimental Results(Radius and Percentage of
Critical Gates)
50
Ave. of Critical Gates for Five Circuits
45
of Critical Paths 500
40
35
30
25
20
15
10
Radius
1
3
5
7
10
15
Five Circuits (s13207, s15850, s35932, s38417,
s38584)
23
Experimental Results(Switching Activity
Reduction Results)
20
Ave. Reduction Ratio for Five Circuits
18
16
14
12
WSA
10
(previous estimation)
8
CCT
6
4
2
0
Random
Proposed
ITC 2005
Five Circuits (s13207, s15850, s35932, s38417,
s38584)
24
Experimental Results(Maximum Path Delay)
Circuit s38584
(ns)
4.200
4.100
4.000
3.900
Proposed
Random
ITC 2005
Original
Library ARM(Artisan)/TSMC CLN90G 1.0V
SAGE-X Critical path PrimeTimeTM Layout SoC
EncounterTM IR-drop VoltageStormTM
25
Conclusions

• IR-drop-induced malfunction
• Causing yield loss
• Critical-Path-Aware X-Filling
• Satisfy new paradigm of X-Filling
• Reduction of critical capture transition (CCT)
• Experimental results
• Could reduce CCT more effectively than the
  previous method
• Could reduce path delay caused by IR-drop

previous
Whole Circuit
indirect
IR-Drop-Induced Malfunction
X-Filling
Critical Paths
direct
proposed