Basic HC11 Instruction Set

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Basic HC11 Instruction Set
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HC11 Instructions

• Instructions consist of
• Opcode - Tells what kind of instruction
• Operands - 0 to 3 parameters for the instruction

• 0 ABA - add acc. B to acc. A
• 1 LDAA 34 - load the value from mem34 into
  acc. A
• 2 BSET 02, 5 - set bits 0 and 2 of mem2
• 3 BRCLR 82, 4, 14 - Branch to 14 if bit 2 of
  mem82 is zero

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Instruction Families

• Instructions come in families
• Accumulator-based machine means that registers
  are specified in the instruction itself (inherent)

• LDAA - load acc. A
• LDAB - load acc. B
• LDD - load double acc. D (A and B together)
• LDS - load stack pointer SP
• LDX - load index reg. X
• LDY - load index reg. Y
• These are collectively known as the LOAD
  instruction

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Adding Instructions

• The ADD family adds either a register, immediate,
  or memory value to an accumulator
• ABA - add acc. B to acc. A
• ABX - add acc. B to index reg. X
• ABY - add acc. B to index reg. Y

• ADDA 13 - add the number 13 to acc. A
• ADDB 64 - add mem64 to acc. B
• ADDD 10,Y - add mem10Y,10Y1 to acc. D
• If Y 30 and mem40 12, mem41A2, then
  12A2 is added to D

• If the ADD produces a carryout, the C cc is set
  to 1

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Adding with Carry, Subtracting

• The ADC instructions add the operand and the
  carry bit to the accumulator
• Allows the addition of numbers larger than 16 bits

• ADCA 72 - adds 72 carry bit to acc. A
• ADCB 0112 - adds mem0112 carry to acc. B
• We will explore using the carry bit later

• Subtraction is similar to adding
• SBA, SUBA, SUBB, SUBD, SBCA, SBCB

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Writing to Memory

• We write to memory by storing data

• The STORE family takes care of this
• STAA 12,Y - stores acc. A at mem12Y
• STAB 3412 - stores acc. B at mem3412
• STD 102 - stores acc. D at mem102,103

• STX 3FF2 - stores X at mem3FF2,3FF3
• STY 18,X - stores Y at mem18X,18X1
• STS 44 - stores SP at mem44,45

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Machine Instruction Format
Note that some instructionsare of different
lengths
Assuming that the LDAA is at memory location
2000, heres what wesee in memory
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What does it take?
Instruction Machine Language
LDAB 15,Y
18 e6 0f

• First, the CPU must read the instruction from
  memory.
• This takes three cycles since only one byte can
  be read during a cycle
• Read mem2002, mem2003, mem2004

• Second, the CPU must compute the effective
  address by adding 15 to to the value of index
  register Y
• This takes another cycle
• No action on the memory bus

• Third, the CPU must read memory 15 Y
• This takes yet another cycle
• Read mem15 Y

• Thus, this instruction takes five cycles

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LDA Load Accumulator
LDA Instruction Details (p. 706)
Accumulator specified gets a value from memory
Operation ACCX lt-- (M)
DescriptionLoads the contents of memory
into the 8-bit accumulator. The condition codes
are set according to the data.
Condition Codes and Boolean Formulae S X
H I N Z V C- - - - ô ô 0 -
N and Z ccs may be set or cleared, V is always
cleared
N R7 Set if MSB of result is set cleared
otherwise. Z R7 R6 R5 R4 R3
R2 R1 R0 Set if result is 00 cleared
otherwise. V 0 Cleared
Source Forms LDAA (opr) LDAB (opr)
There are two forms of LDA One for each of the
accumulators
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Addressing Modes, Machine Code, and
Cycle-by-Cycle Execution LDAA (IMM) LDAA
(DIR) LDAA (EXT) LDAA (IND,X) LDAA
(IND,Y) Addr Data R/W Addr Data R/W Addr Data R/
W Addr Data R/W Addr Data R/W1 OP 86 1 OP 96 1 OP
B6 1 OP A6 1 OP 18 12 OP1 ii 1 OP1 dd 1 OP1 h
h 1 OP1 ff 1 OP1 A6 13 00dd (00dd) 1 OP2 ll
1 FFFF 1 OP2 ff 14 hhll (hhll) 1 Xff (
Xff) 1 FFFF 15 Yff (Yff) 1
LDA Instruction Details (p. 706)
OP - Operation fetch - reads memory to get
operation
ff - offset for indexed mode
FFFF --- - no memory activity this cycle (just
thinking)Also found as OP1 --- OP2 ---
ii - immediate data
dd - memory address for direct mode
hhll - memory address for extended mode
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Addressing Modes, Machine Code, and
Cycle-by-Cycle Execution Cycle LDAA
(IMM) LDAA (DIR) LDAA (EXT) LDAA (IND,X) LDAA
(IND,Y) Addr Data R/W Addr Data R/W Addr Data R/
W Addr Data R/W Addr Data R/W 1 OP 86 1 OP 96 1 O
P B6 1 OP A6 1 OP 18 1 2 OP1 ii 1 OP1 dd 1 OP1
hh 1 OP1 ff 1 OP1 A6 1 3 00dd (00dd) 1 OP2
ll 1 FFFF 1 OP2 ff 1 4 hhll (hhll) 1 X
ff (Xff) 1 FFFF 1 5 Yff (Yff) 1

LDA Instruction Details (p. 706)
861000 0110
B61011 0110
A61010 0110
A61010 0110
961001 0110
Cycle LDAB (IMM) LDAB (DIR) LDAB (EXT) LDAB
(IND,X) LDAB (IND,Y) Addr Data R/W Addr Data R/W
Addr Data R/W Addr Data R/W Addr Data R/W 1 OP C
6 1 OP D6 1 OP F6 1 OP E6 1 OP 18 1 2 OP1 ii 1 O
P1 dd 1 OP1 hh 1 OP1 ff 1 OP1 E6 1 3 00dd
(00dd) 1 OP2 ll 1 FFFF 1 OP2 1 4 hhll
(hhll) 1 Xff (Xff) 1 FFFF 1 5 Yf
f (Yff) 1
C61100 0110
D61101 0110
F61111 0110
E61110 0110
E61110 0110