Introduction to HC11 Main Timer Functions

1
Introduction to HC11 Main Timer Functions

• ME 6405 Introduction to Mechatronics
• Turner Howard
• Susan Knueven
• Jason Lawrence
• October 19, 2000

2
You will learn how to

• prescale the main timer counter
• record the time an event occurs
• take an action at a specific time
• handle counter overflows
• use Real-Time Interrupts
• use the Pulse Accumulator to
• count events
• measure the duration of an event

3
Road Map for Presentation

• General Description of Main Timer
• Input Capture Concept
• Output Compare Concept
• Real-Time Interrupt (RTI) Function
• Pulse Accumulator

Turner
Jason
Susan
4
General Description of Main Timer

• Central element16-bit free running counter
• At reset counter starts from 0000 and counts up
  continuously
• When FFFF is reached, counter rolls over to
  0000
• May be read at any time using a double-byte
  instruction like LDD or LDX
• Cannot be written or reset during operation

Bit 15
-
Bit 8
100E
-
-
-
-
-
TCNT
100F
Bit 7
Bit 0
-
-
-
-
-
-
5
Counter Prescaler

• Allows 4 clocking rates of the timer counter
• E-Clock rate divided by 1, 4, 8, 16
• At reset the default prescale factor is 1
• Must be set during the first 64 E-Clock cycles
  after reset

6
Changing the Counter Prescaler

• Trade-off between timer resolution and timer range

7
Counter Overflows

• Timer overflow flag (TOF) status bit set each
  time the counter rolls over from FFFF to 0000
• TOF status bit can generate an automatic
  interrupt request by setting the timer overflow
  interrupt (TOI) enable bit

8
Input Capture Concept

• Used to record the time an event occurs
• When an input signal is received, the time is
  stored in memory by capturing the contents of the
  free-running counter

9
Features of Input Capture Function

• 16-bit registers
• Input edge-detection logic
• Interrupt generation logic

10
Input Capture Registers

• Three 16-bit input capture registers are
  available
• Each register has a corresponding timer input pin
  (TIC1-TIC3) located on Port A pins PA0-PA2
• When an edge is detected at a timer input pin,
  the current value of the free-running counter is
  stored in the corresponding input capture
  register

11
Input Capture Registers (cont)
Bit 15
-
Bit 8
1010
-
-
-
-
-
TIC1
1011
Bit 7
Bit 0
-
-
-
-
-
-
Bit 15
Bit 8
1012
-
-
-
-
-
-
TIC2
1013
Bit 7
Bit 0
-
-
-
-
-
-
Bit 15
Bit 8
1014
-
-
-
-
-
-
TIC3
1015
Bit 7
Bit 0
-
-
-
-
-
-

• Can be read at any time as a pair of 8-bit
  registers using instructions like LDD or LDX
• Cannot be written by software

12
Input Edge-Detection Logic

• Used to select which edge of an input is detected

13
Interrupt Generation Logic

• Input capture status flags are automatically set
  to one each time a selected edge is detected
• Input capture interrupt enable bits

14
Application of Input Captures

• Period or frequency measurement
• Capture the time of two successive rising or
  falling edges (see Ref. Manual 10-41)
• Example code
• Pulse width measurement
• Capture the time between two adjacent pulses (see
  Ref. Manual 10-44)

15
Period Measurement Example Code

• FIRST EQU D000 DEFINE A 2-BYTE LOCATION TO
  STORE FIRST EDGE
• PERIOD EQU D002 DEFINE A 2-BYTE LOCATION TO
  STORE PERIOD
• ORG C000
• LDX 1000
• LDAA 10
• STAA 1021 EDGE DETECTION FOR IC1 SET TO
  RISING EDGES
• LDAA 04
• STAA 1023 CLEARS ANY OLD FLAGS FROM IC1F
• LOOP1 BRCLR 23,X 04 LOOP1 LOOP HERE UNTIL
  FIRST RISING EDGE IS DETECTED
• LDD 1010 READ TIME OF FIRST CAPTURE
• STD FIRST STORE FIRST CAPTURE VALUE
• LDAA 04
• STAA 1023 CLEAR THE IC1F FLAG BEFORE NEXT
  EDGE
• LOOP2 BRCLR 23,X 04 LOOP2 LOOP HERE UNTIL
  NEXT RISING EDGE IS DETECTED
• LDD 1010 READ TIME OF SECOND CAPTURE
• SUBD FIRST FIND THE TIME DIFFERENCE BEWTEEN
  EDGES
• STD PERIOD STORE THE RESULT AS THE PERIOD

16
Measuring Long Periods Using Counter Overflow

• Extending the range of the 16-bit counter with an
  8-bit software counter
• Software keeps track of counter overflows
• Creates a 24-bit counter
• Time values are stored as 3-byte numbers
• (see Ref. Manual 10.3.5 and page 10-46)

17
Application of Input Captures (cont)

• Can be used as a time reference for an output
  function.
• Input Capture records the event time
• Offset representing time delay is added to the
  input capture and stored to an output compare.
• Both input captures and output compares are
  referenced from the same counter, so software
  latencies do not affect the accuracy to time
  delay (See Ref. Manual section 10.3.6).

18
Other Uses of Input Capture Pins

• Can be used as general purpose input pins when
  the timer functions are not needed
• Logic levels can be read even if the
  input-capture function is enabled
• Can serve as flexible interrupt input pins
• Have some advantages over the IRQ pin
• See Ref. Manual section 10.3.7

19
Output Compare Basic Concept
16 Bit Register Stores a Number 5 possible
Registers to store this number Comparator
checks Number against Free Running Counter (TCNT
Register) Really 5 comparators-one for each
number This is done in hardware, no processor
time used When Counter matches TOCx Register,
it triggers an event
20
What Event is triggered?

• Three Possibilities
• Changes the ouput of one or several of the pins
  in Port A
• Set a Flag in TFLG Register
• Cause an Interrupt

21
Output Compare causes Port A Pins to change state
(Part I)

• Output Compares 2 to 5
• Each Output compare controls a SINGLE PIN

22
Output Compare causes Port A Pins to change state
(Part II)

• Output Compares 2 to 5
• TCTL1 Register Controls How Each Pin Changes

TCTL1 1020
23
Output Compare causes Port A Pins to change state
(Part III)

• Output Compare 1
• Causes 5 Port A pins to change simultaneously
  (PA3-PA7)
• Notice PA3-PA6 are also used by Output Compares
  2-5

OC1M Register determines which Port A Pins will
be Controlled by Output Compare 1
PA7
PA6
PA5
PA4
PA3
OC1M 100C
OC1D Register sets value to be written to Port A
pins selected in OC1M
OC1D 100D
24
Output Compare Causes Flag to Be Set (Part I)
When Output Compare is successful it sets
corresponding Flag in TFLG1 Control Register
Software must constantly poll TFG1 register to
check for flags
25
Output Compare Causes Flag to be Set part (II)
You clear the Flag by writing a 1 to the
corresponding Bit in TFLG !?!
You Must clear the Flag after it is set
Use LDAA, STA, BCLR commands to write 1 to Flag
But DONT USE BSET!!!!
Example Output Compare 2 sets flag...but before
program could clear OC2F Output Compare 3 sets
flag goal is to clear OC2F without clearing OC3F
26
Output Compare Causes a Interrupt
Output compare will cause an interrupt when
corresponding bit in TMSK1 is set
27
Measuring Long Intervals Problems with Overflow
Bit
You must measure this length of time
t
Record Start Time
Record End Time
time
t
But I only have this much time to record last
overflow then I need to record the end time!
This is where timer rolls over (overflow)
tTEND-TSTART( of overflows)(Toverflow)
28
Forced Output
If you need to change state of Port A Pin BEFORE
output compare occurs
Use Forced Outputsoftware triggers compare to
occur and Pin A will change state accordingly
29
Example-Creating A Pulse Width Modulated Signal
with OC2
This is example 10-7 in the book all examples
are included on the disks that came with your
EVB board
b
a
Goal
30
Initializations
INZ7 LDS 0047 Top of User's stack area on
EVB LDAA 7E Jump (extended) Opcode STAA
PVOC2 OC2 Pseudo Vector LDX SV7OC2 Address of
OC2 service routine STX PVOC21 Finish jump
instruction to OC2 routine LDX REGBAS Point to
register block
Set Interrupt vector so it jumps to SVOC2 when
Output Compare 2 is successful
31
Initializations II
LDAA PWMDC1 Calculate OC2 high
time LDAB PWMP1P 1 of period MUL PWMP1P
duty cycle high part of period STD OFFHI Save
high offset LDAA PWMP1P 1 of period LDAB 100 MU
L 100 PWMP1P period SUBD OFFHI period -
high time low time STD OFFLO Store low offset
Length of time output is High (a)
Duty Cycle Length of 1 of
periodOFFHI Length of Full Period-OFFHIOFFLO
Length of time output is Low (b-a)
32
Initializations III
LDAA 11000000 OM2OM1 11 for set pin
high STAA TCTL1,X First OC2 starts first high
time LDD 0000 STD TOC2,X Start first PWM
period at TCNT0000 LDAA 40 STAA TFLG1,X OC2F
1 to clear any old OC2 flag STAA TMSK1,X then
OC2I1 to enable OC2 interrupt CLI BRA From
now on OC2 interrupt runs PWM

• First Output Compare 2 will write a 1 to PA6 Pin
• First Output Compare will happen at TCNT 0000
• Clear old OC2 Flags in TFLG1
• Enable the OC2 interrupt and Loop till receive
  interrupt

33
Interrupt Service Routine
SV7OC2 LDX REGBAS Point to register
block BRCLR TCTL1,X 01000000 ADDLO See which
half of cyc LDD OFFHI High part so we will
add
OFFHI to OC2 BRA UPOC2 ADDLO LDD OFFLO L
ow part so we will add
OFFLO to OC2 UPOC2 ...
?If last Output Compare wrote 0 to PA6 (ie. TCTL1
was 10000000) then load Accumulator D with
OFFLO ?If last Output Compare wrote 1 to PA6
(ie. TCTL1 was 11000000) then load Accumulator
D with OFFHI
34
Interrupt Service Routine II
UPOC2 ADDD TOC2,X Add to last compare
value STD TOC2,X Update OC2 (schedule next
edge) LDAA TCTL1,X Change OL2 to setup for next
edge EORA 01000000 Inverts OL2
bit STAA TCTL1,X Update control
reg BCLR TFLG1,X BF Clear OC2F RTI Return
from OC2 service

• TOC2TOC2OFFHI or OFFLO
• TCTL1 ? 01000000 TCTL1
• Clear OC2 Flag

35
Real-Time Interrupt

• Generates hardware interrupts at a fixed rate
• Free-running counter cannot be interrupted
• One of four rates- software selected
• One flag- set at the user determined rate
• Flag must be cleared after it is used, especially
  when using interrupts or a system lock up will
  occur.

36
RTI Registers

• TMSK2 1024
• Real-Time Interrupt Enable
• TFLG2 1025
• Real-Time Interrupt Flag
• PACTL 1026
• Real-Time Interrupt Rate Selects

37
Real-Time Interrupt Rate Selects
For 8MHz Crystal Frequency (2MHz E Clock)
38
RTI Example Oven Control

• ExampleUsing a 33 ms RTI interrupt, the slave
  board should measure the oven temperature and
  save the value in a global variable. It should
  turn the heater on if the oven temperature is
  below the set point, and turn the heater off if
  the oven temperature is above the set point.

39
Pulse Accumulator Overview

• 8-bit Counter
• Incremented by edge on pin
• Used
• to measure duration of pulse
• number of events

40
Key Things to Know

• Can be read or written at any time
• 2 Modes
• Event Counter
• Gated Time Accumulation
• PAI Pin Port A Pin 7
• Registers

41
Pulse Accumulator Registers

• PACNT 1027
• 8 Bit PA Count
• PACTL 1026
• Data Direction for PA7 Pin
• PA Enable
• PA Mode
• PA Edge

42
Pulse Accumulator Registers

• TFLG2 1025
• PA Overflow Flag
• PA Input Edge Flag
• TMSK2 1024
• PA Overflow Interrupt Enable
• PA Input Edge Interrupt Enable

43
Register Settings

• DDRA7 0Input, 1Output
• PAEN 0Disabled, 1Enabled
• PAMOD 0Event Counter, 1Gated Time
• PEDGE
• Event Counter 0Falling Edges, 1Rising Edges
• Gated Time 0Inhibit Gate level is zero,
  1Inhibit Gate level is one

44
Register Settings

• PAOVF 0No Overflow, 1Overflow
• PAOVI 0Polling, 1Interrupt-Driven
• PAIF 0No Interrupt, 1Interrupt
• PAII 0Polling, 1Interrupt-Driven

45
Event Counting Mode

• PAMOD0
• Counts Active Edge of PAI pin
• Example (PACNT0PAEN1PEDGE1)

46
Event Counting Example

• A light emitter/detector pair can be used in an
  assembly line to count the number of parts going
  by.

47
Gated Time Accumulation Mode

• PAMOD1
• Free-running E-clock divided by 64
• Subject to PAI pin being active

48
Gated Time Example

• PACNT0PAEN1PEDGE1
• PEDGE1 means inhibit gate is 1 (inhibit
  counting when PAI is 1)

49
Pulse Width Measurement

• Common use of Gated mode
• Measure duration of single pulses
• Easier than with Input Capture
• Counter is zero before pulse starts
• After pulse, pulse time directly read (need
  starting and ending count for input capture)

50
ExampleInterrupt at Specified Time

• Gated Time Accumulation (PAMOD1)
• Set Pulse Accumulator to interrupt after 5ms
• Steps
• Calculate time for one E/64 cycle
• Divide delay by time for one E/64 cycle
• Take 2s complement and store in PACNT
• When input goes to active level, counter will
  increment until overflow

51
Assembly Code Initialization to Count Negative
Edges

• LDAA BIT54HI
• STAA TFLG2 /Clear previous interrupts/
• LDAA TMSK2
• ORAA BIT54HI /Enable pulse accumulator
  interrupts/
• STAA TMSK2
• LDAA PACTL
• ANDA BIT7_4LO /BIT7_4LO 00001111/
• ORAA BIT6HI
• STAA PACTL /Select Event,Falling
  Edge,DDRA7-Input/