GSFC Integrated Avionics (SE Seminar Briefing)

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GSFC Integrated Avionics(SE Seminar Briefing)

• Jaime Esper / 592
• Jaime.Esper_at_nasa.gov
• 11/5/2007

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GSFC Integrated Avionics

• Integrated avionics refers to the space mission
  end-to-end and commands either internally, or
  between users/electronic system (software and
  hardware components) used to exchange and process
  data systems either on the ground or in space.
• The Mission Integration and Demonstration
  Facility (MIDF) has been proposed as a means to
  accomplish the integration of avionics components
  within GSFC under a single roof. It is composed
  of at least three major parts The
  Communications, Standards and Technology
  Laboratory (CSTL), The Goddard Mission Systems
  Evolution Center (GMSEC), and the Vehicle
  Avionics Integration Laboratory (VAIL).
• MIDF improves our abilities in several areas,
  including evaluation and verification of
  end-to-end architectures, systems, and standards,
  and our ability to streamline integration, test,
  and processing of spacecraft.

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Mission Integration and Demonstration Facility
Overview

• The MIDF combines all elements of a space mission
  within a single roof
• Includes Space Segment Components                 
                           On-board electronics
  (traditional avionics)         - Command Data
  Handling / Navigation Attitude Control        
  - Communications InterfaceFlight
  softwareInterface Standards (plug-and-play
  preferable)
• Includes Ground Segment ComponentsGround
  system        - Mission Control        -
  Interface to Science Center or distributed
  facilities        - World-Wide-Web leverage for
  distributed operations (VPN) and/or public
  access        - Communication interfacesGround
  station network (incl. TDRSS, GSTDN)Interface
  Standards (plug-and-play)

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MIDF is a Plug-and-Play Facility (Long-Term
Perspective)

• The aerospace community is moving toward
  plug-and-play open interfaces (non-proprietary).
  This allows for cross-platform compatibility and
  enhanced customer choices.
• Flight projects would bring their on-board
  electronics and application software for
  integration and test within an end-to-end mission
  environment. Lower-layer software,
  communications infrastructure, and
  (plug-and-play) interfaces will be already in
  place.
• No need to re-create ground segment components.
  These will be already available as well.

Depending on the approach chosen, these items
may be integrated into the MIDF from a remote
location.
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MIDF Laboratories

• Incorporate
• Mission Control Lab / GMSEC (MCL)
• Vehicle Avionics Integration Lab (VAIL)
• Communications Standards Technology Lab (CSTL)
• Other Laboratories as technology requires

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A Mobile Implementation of VAIL

• VAIL can have several implementations. One
  possibility is to use a Rover as a platform on
  which to integrate flight-like avionics systems.
• Its mobility serves an operational demonstration
  that is in-line with the MIDF approach realistic
  scenarios on which to test mission-level systems.
• One such demonstration can be the operation of
  the Rover (VAIL) in a hostile environment (South
  Pole), commanded using the GMSEC framework,
  through the lines and interfaces of the CSTL.
• This scenario also serves as a means to
  demonstrate the South Pole Delay-Tolerant Network
  (DTN) a developing protocol intended to bridge
  between two network regions by translating
  between incompatible network characteristics and
  acting as a buffer for mismatched network delays.
• This has been developing to service the US
  Station at the Geographic South Pole and is
  applicable to future Exploration applications of
  local and wide-area networks using wireless and
  other means of communication.

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SpaceCube Robotic Presentation

• by Gordon Seagrave
• GSFC [phone]

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PROCESSOR (SCuP) SLICE OVERVIEW
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What is SpaceCube?

• Completely Reconfigurable Super Computer for
  Space
• Small footprint 4 x 4 x 3 inches
• Low Power
• High Processing Engine 4 x PPC405 _at_ 450MHZ
• Commercial parts Low cost
• Rapid Development Digikey parts and MiniCube
  fit onto flight board pads
• Configurable I/O LVDS/SpaceWire or RS422
• Flexible / Stackable Architecture

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Core Space Cube Capabilities

• SPECIFICATIONS
• CENTRAL PROCESSORS
• 4 x 450 MHz PowerPC 405, 32-bit RISC processors
• 2 x Xilinx XC4VFX60
• Redundant to handle SEFI
• 32K bytes of secondary (L2) on-die cache
• Common Processor Features are-
• 700 DMIPS RISC core
• 32-bit Harvard architecture
• 16 KB 2-way set-associative instruction and data
  caches
• Auxiliary Processor Unit (APU) controller
• 1.2V core voltage
• RECONFIGURABLE RESOURCES
• 2 x 56,880 logic cells
• 2 x 25,280 slices
• 2 x 4,176 Kb block RAM
• 232 18K block RAMs
• Example Helion AES core
• 447 slices, 10 block RAM, 2548Mbps performance

ETHERNET CAPACITY 8 x Ethernet Media Access
Controllers IEEE 802.3 compliant 10, 100, 1000
Mb/s Supports MII, GMII Does not use any system
gates. DIGITAL SIGNAL PROCESSING 128 XtremeDSP
Slices 18-bit by 18-bit, two's complement
multiplier with full precision 36-bit result,
sign extended to 48 bits. FLASH EPROM 1 Gbyte of
Flash EPROM application storage Flash has
separate power switching. Allows Flash to be
powered off when not in use. ROM 256 Mbyte of
ROM application storage backup for
Flash SOFTWARE SUPPORT Support for Linux,
VxWorks WindRiver MontaVista GNU GCC Compiler
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Core Space Cube Capabilities
SERIAL INTERFACES 32 x LVDS serial pairs Support
Ethernet, SpaceWire, or custom interface. 16550
compatible UARTs Aeroflex LVDS drivers and
Receivers RS422 can be substituted for LVDS if
desired STACKING CONNECTOR INTERFACE Airborne
Connector 72 pins Design uses no backplane or
motherboard. Low speed internal bus 400Kbps
Redundant I2C High speed bus TBD
Redundant Power Pins 3.3V, 5V RAD-HARD
SCRUBBER UT6325 RadHard Eclipse FPGA 320,000
usable system gates 24 dual-port RadHard SRAM
modules RadHard to 300K rad(Si)/sec OTHER
PERIPHERAL INTERFACES Available through stacking
connector by additional card slices Low Voltage
Power Converter card slice Same board size as
processor Provides low voltages from spacecraft
bus voltage Has 1553 interface, transformers and
signal drivers
ELECTRICAL SPECIFICATION 21V to 35V voltage input
through optional low voltage power converter card
slice 5V_at_TBDA (typical at 450 MHz with 1 Mbits
SDRAM) 3.3V_at_TBDA 2.5V_at_TBDA all voltages are
tolerant to 10 / -10 SAFETY SDRAM power is
switched separately to handle any potential
latchup conditions. ENVIRONMENTAL
SPECIFICATION -100C to 55C (operating)
(TBR) -40C to 85C (storage) 10 to 90
Relative Humidity, non-condensing (storage)
MECHANICAL SPECIFICATION 4 inches x 4 inches
(PCB) Box slice TBD inches x TDB inches single
board, double sided I/O connectors 72 pin,
Airborne Stacking 2 x 37 pin LVDS
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Completely Reconfigurable
PPC Operating System PPC Application Code
RISC uP Application Code
Xilinx FPGA Personality
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SpaceCube Housing

• MINIMUM Avionics Configuration.
• Processor Slice (SCuP) is a CDH system on a 4 x
  4 inch card.

LVPC 2
SCuP 1
SCuP 2
LVPC 1
RNS BD

• Minimum Configuration 4 x 4 x 3 inches
• Scup
• LVPC

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Stacked Architecture Allows Endless Flexibility

• SpaceCube uses a stacked architecture
• composed of cards or slices connected via a
  connector running the length of the stack
• Slices can be made redundant and the stacking
  architecture allows any slice to communicate with
  any other slice thus allowing card level
  redundancy.
• Custom Slices Stack onto the SpaceCube
• Processor and LVPS Slices
• Small card size (4x4 inches) means mass is
  minimal. (lt2Kg for minimum configuration)

Processor
Project Module
Processor
LVPC
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Option1 PPCs work on same task
The PPCs may act as one engine performing a task
together where the outputs are voted
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Option 2 PPCs Perform Different Tasks
The PPCs may act as 4 unique engines performing
4 unique tasks where the outputs may not be voted.
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PPC405 Supported Operating Systems

• VxWORKS
• BlueCat Linex
• RTEMS

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Processor Performance
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Sand Box Resources
4 x
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Implementation of Space Cube within a Rover
POWER
Heaters
Un-switched Power Services
SPACE CUBE (SC) AVIONICS
Power Electronics
Additional Hardware (per Rover Specification)
Battery
Sensors
Low Voltage Power Converter Discretes
Slice 1
Power
Actuators
CMD and TLM Lines
Slice 2
Firewire (1394a)
Reconfigurable Logic
Sensors
Redundant Serial busses Two high speed 100 Mbps
links / Two low speed 400 Kbps links
CDH Nav Processor
Ethernet/ Spacewire
Actuators
Cam 2
Cam 1
Navigation Cameras
Slice 3
MIL-STD-1553
Comm. Interface
ITOS / ASIST
Simulated RF Com Interfaces (Ethernet)
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Mixed Rate Ethernet Processing
Example of Mixed Rate Ethernet Processing
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Xilinx Ethernet Hub Processing
Each PPC has access to 2 RadHard Ethernet MACs
10MBit
100MBit
Example of dual speed Ethernet Implementation
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SpaceCube PackagingProcessor Slice and CCA
PROCESSOR PWB EDU, 2098673

• Designed per IPC-2222 and Fabricated per IPC-6012
• Multi-layer (18 layers) board material
  construction per IPC-4101
• PWB, 2098673, size 4.00W x 4.00L x .093T (inch)
  (Polyimide-glass laminate)
• Up to 2 oz top bottom, and internal signal
  ground planes utilized for thermal management of
  components.
• Maximum component heights 0.79 inch (primary
  side), and 0.21 inch (secondary side)

Primary Side

• External interface thru two MIL-DTL-83518
  (Micro-D) connectors
• The Processor board is supported by 2 stiffeners
  and 2 integral stand-offs.

Secondary Side
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SpaceCube Packaging Power Slice
Assembly(contains DCC and LVPC Boards)
LVPC Board
DCC Board
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SpaceCube Lite Overview
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SpaceCube Lite

• Low Cost
• High Speed Processing Engine
• Low Power
• 12V power source
• Battery
• Wall Wort
• Rugged

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Delay/Disruption Tolerant Networking (DTN)

• Protocols to provide the benefits of networking
  in disrupted and delayed environments
• Space applications Speed of light delays and
  scheduling/coverage delays (NASA/Interplanetary
  Network (IPN))
• Defense applications (DARPA)
• Commercial applications intermittent wireless
  links
• Very active area of research within Universities,
  DARPA, and NASA
• See http//www.dtnrg.org

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An End-to-end Path using DTN
custody transfer
internet a
internet b
BP
BP
BP
TCP
IP
SONET
fiber
Network of internets spanning dissimilar
environments
Source Scott Burleigh (JPL)
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Store-and-Forward Networking
Relay stores data while not in view of Earth
Disruption Tolerant Networking (DTN) is an effort
to develop and standardize a message-based,
store-and-forward system with reliability,
security, and quality of service.
Relay transmits data when in view of Earth
Relay Range
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Polar Robot DTN Demonstration Scenario
Lunar Relay Satellite (LRS) TDRS
Ground Station WSC
Lunar Communications Terminal (LCT) McMurdo
Station
Mission Control GSFC
Lunar Rover Robot
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Polar Robot Demonstration Network Topology
JHU DTN BA
DTN BA
Crater Hill Network
Rover
McMurdo DTN BA
UMD DTN BA
Rover Laptop with DTN BA
Internet
McMurdo Network
DTN BA
CSTL DTN BA
Dry Valley Network
Rover
Rover Laptop with DTN BA