Description and Analysis of MULTIPLIERS using LAVA

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Description and Analysis ofMULTIPLIERSusingLAVA
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Today

• Describe the most common multiplier circuits
• In general
• As Lava descriptions
• Analyze them using Lava
• Self optimizing descriptions
• Time and size estimations

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Lava advantages

• Efficient description of very complex structured
  circuits
• Automatically generic description (in contrast to
  e.g VHDL)
• Efficient use of formal verification
• Inheritance of the power of Haskell

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Binary multiplication

• All algorithms use the sum of partial products
  method
• Possible trade-off
• Many PPs Easier generation
• Fewer PPs Complex generation

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Binary multiplication

• Decomposition of the multiplier

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Binary multiplication

• Partial product selection method
• Pi Si ? N (shifted to the same position as
  Si )
• Example

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Binary multiplication

• Two basic steps
• Generation of partial products (PPG)
• Summation of partial products
• Several methods exitst for each step
• Famous Booth, Wallace
• Goal
• To be able to combine any method for the first
  step with any method for the second step

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Interface

• All PPs start from position 0 (shift by padding
  zeroes)
• Use adders whose result has the same length as
  the longest input (no carry-out)
• When carry-out is needed (only 1-bit selection),
  pad with one zero after

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Simple PPG (1-bit selection)
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Bit multiplier
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Carry-propagate adder
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Linear array summation
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Adder tree summation
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Simple multipliers
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Booths algorithm (s-bit selection)

• The number of PPs is m/s
• s-1 adders are used in the selection

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Improved Booth 2

• Booth 2 selects part. prod. values from 0,N, 2N,
  3NBUT, 3N 4N N
• So, instead of 3N, select N
• The next part. prod. selection has to compensate
  for this

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New selection method
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Improved Booth s

• The number of PPs is m/s1
• s-2 adders are used
• The negation of PPs can easily be integrated into
  the selection procedure

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Improved Booth s
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The carry-save adder
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The carry-save array
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Speed up summation with faster adders
(logarithmic)

• Linear array has several equal-length critical
  paths? All adders need to be replaced
• The carry-save array has only ONE critical path?
  Replace only the final CPA

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Logarithmic adder (Ladner Fisher)
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Wallace tree
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Wallace tree

• Sums in O(log m) steps

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Reducing hardware

• All circuits have used lots of constant bits,
  which need unnecessary hardware
• Circuits operating on constant bits can be
  reduced
• Sufficient to make the reduction in the basic
  gates (inv, and, nand, or, nor, xor, xnor)
• The reduction of the larger circuits follows
  automatically

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Interpretations

• Standard
• Symbolic
• Non-standard

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Self-reducing gates

• Constant bits low, high
• Everything else is variable
• var a
• inv high

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Reduction of larger circuits
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Time estimation
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Size estimation

• Problem with sharing

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Redifinition of basic gates
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Redefinition of AND
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Estimation functions
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Estimations
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Results

• Different selection group lengths with
  linearArray summation

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Results

• Wallace summation instead

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Results

• Different summation networks with simple PPG

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Results

• Regular summation networks

addTree carrySave
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Limitations of the estimations

• Wiring delays
• Needs layout information
• Fan-out
• Several inputs connected to the same output ?
  slower signal
• Only standard gates are used
• Better techniques exist for e.g full adders