Diapositiva 1

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Digital Full Calibration Techniquesfor Pipeline
ADCs
Antonio J. Ginés Eduardo J. Peralías
Adoración Rueda rueda_at_imse.cnm.es
Intituto de Microelectrónica de Sevilla- CNM
(CSIC) Spain
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Contents

• Motivations
• Pipeline ADC Error Sources
• Foreground vs. Background Calibration
• Noise Correlation-based Calibration
• Digital Full calibration Techniques
• Background and Foreground
• Digital Hardware Implementation
• Simulation results
• Silicon demonstrator
• Conclusions

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Motivations

• Pipeline ADC

CALIBRATION
MDAC ERRORS
Required in high-speedhigh resolution
applications
Relax the analogue blockspecifications
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Pipeline ADC Error Sources

• Sub-ADC Errors
• Digital Correction
• There is not performance degradation

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Foreground vs. Background Calibration

• Miscalibration
• Temperature changes
• Power supply
• Component aging
• ....

NOISE CORRELATION-BASED
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Noise Correlation-based Background Calibration (I)
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Noise Correlation-based Background Calibration
(II)
STATE OF THE ART
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Noise Correlation-based Background Calibration
(III)
STATE OF THE ART
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Proposed Digital Full Calibration

• Estimation and correction
• SUC MDAC gain and non-linear errors
• The global gain error associated to the back-end
  stages

• Noise correlation-based algorithm
• This system uses a noisy sub-ADC controlled by a
  digital signal N
• It modulates Z2 obtaining an additive error code
  by mean of a statistical averaging process with
  low cost implementation

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Proposed Digital Full Calibration
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Additive Error Codes
Gain Error
Uncalibration
Non-linear Errors
Calibration
Missalingment betweenlinear segment
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Error Code Estimation Noisy sub-ADC
W1 (c1) Measurements
The signal N modulates theSUC output residue
E N 0 E x N 0
Foreground and Background Applications
Reference Shifts Compatible with Digital
Correction
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Digital Hardware Implementation

• Digital Resources
• 1 Accumulator
• 2 Memories
• Adders

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Zone Factor Signal (ZFS) Generation
SECOND ORDER EFFECTS
ROBUST GENERATION OF THE ZFS
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Alternative Noisy sub-ADC
Alternative Architecture
Use Extra Comparator / s
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Simulation Results (II)

• 12-bit Pipeline ADC. Configuration 3 (SUC)
  9x1.5

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Silicon Demonstrator

• 15-bit 50MHz Background Calibrated Pipeline ADC
  in 0.18um 1-poly 6-metal CMOS process

Features Configuration7x3 Background
Calibration SUCs 2 Fs 50MHz, FSR 2Vpp
ENOB 9.8 / 12.1 _at_ 24MHz Power 170mW _at_
2.5V Area 0.9 x 2.0 mm2 INL lt 0.5 LSB _at_ 13-bits
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Silicon Demonstrator
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Currently under test
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Conclusions

• A robust digital full calibration method for
  Pipeline ADCs
• Background and foreground applications
• This system uses a noisy sub-ADC controlled by a
  digital signal N
• It modulates Z2 obtaining an additive error code
  by mean of a statistical averaging process with
  low cost implementation
• We are currently extending the method to stage
  modulated schemes
• Presents four key advantages over known schemes
• It uses a single algorithm for both gain and
  non-linear error calibration
• It requires no significant modifications in the
  analogue blocks of the ADC
• It can be performed without interruption of the
  conversion (Background Calibration), without
  reduction of the dynamic range and without SNR
  degradation
• It has a low cost implementation (High Speed High
  Resolution Multiplier is not required)

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Full Calibration Digital Techniquesfor Pipeline
ADCs
Thank you for your attention