EE5333 Advanced Analog Electronics Design

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EE5333 Advanced Analog Electronics Design
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Setup Cadence in VLSI Lab

• Copy files
• cp r /home/grads/ee5333ta /
• Edit your .cshrc file
• -- Include the following line in your /.cshrc
  file
• source /ee5333ta/.cshrc_ncsu
• -- save close your .cshrc file
• -- source /.cshrc
• Check files
• cd ee5333ta
• ls la
• (should have  .cdsinit, .cdsplotinit, cds.lib
  files and models directory in your ee5333ta
  directory)

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Setup Cadence in VLSI Lab

• 4) Invoke cadence in your ee5333ta directory
• icfb

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Create a library for a new design

• 1) In V irtuoso Window
• File -gt New -gt Library

2) In New Library Window Name OPM Technology
File Attach to an existing technology
library 3) In Attach Library Window Technology
Library NCSU_TechLib_tsmc03d 4) OK
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Create a schematic for a new design

• 1) In Library Manager Window
• File -gt New -gt Cell View

2) In New File Window Libray OPM Cell DIFF
3) OK
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Design A Differential Amplifier
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Placing components

• Add Instance
• Add Wire
• Add Pin

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Add A MOS Instance
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• Browse
• NCSU_Analog_Parts
• N_Transistors
• nmos4
• Width 60u
• Length 1.2u
• Click the right button of the mouse in Virtuoso
  Schematic Editor Window

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Add Components (1/3)

• All basic components are in the library,
  NCSU_Analog_Parts
• There are several groups as shown below

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Add Components (2/3)

• Implement a schematic using the following
  parameters
• Resistance 4KOhm
• NMOS W60um, L1.2um
• Input voltage DC 770mV, AC 1V, phase 0/180
• Supply voltage DC 3.3V
• Use wire to connect all components

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Add Components (3/3)
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Add Pins
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4) Save Check Error If there is no error or
warning, you implement the schematic
successfully.
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Useful Commands Keyboard Shortcuts

• Edit
• Delete
• Rotate
• Move
• Stretch
• Properties -gt Objects
• ESC Cancel command

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Cadence Analog Design Environment
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• Launch -gt ADE L
• Virtuoso Analog Design Environment Window pop up
• Setup -gt Design
• Simulator spectre
• OK

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Setup Model Libraries

• Setup -gt Model Libraries
• Model File (double clicks)
• Select models.scs
• Select C0

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Setup Analyses (1/3)

• Analyses -gt Choose
• In Choosing Analyses Window
• Analysis dc
• DC Analysis Save DC Operating Point
• Analysis ac (see the next page)
• AC Analysis
• -- Sweep Variable
• Frequency
• -- Sweep Range
• Start-Stop
• Start 1K Stop 1G
• -- Sweep Type
• Logarithmic
• -- Select Point Per Decade 10
• -- OK

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Setup Analyses (2/3)
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Setup Analyses (3/3)
After choosing analyses, you could see the dc
ac analyses setting and enable in Virtuoso
Analog Design Environment Window
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Setup Outputs

• Outputs -gt Save All
• In Save Options Window
• -- Select signals to output (save)
• select all
• -- OK

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Run Simulation Check Results

• Simulation -gt Netlist and Run
• Results -gt Annotate -gt DC Node Voltage
• Results -gt Annotate -gt DC Operating Points
• Check your schematic See whats changed
• Tools -gt Calculator

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Plot the output results (1/3)

• Select ac
• Select vf
• Move your mouse to the schematic Window
• Select the net OUTP
• See what happen in your Calculator Window

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Plot the output results (2/3)

• Fill out VF(/OUTP)-VF(/OUTN)
• Select --dB20
• Select -- plot

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Plot the output results (3/3)

• Check the Frequency Response in Graph Window
• Find the 3dB Frequency

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Build the symbol from the schematic

• In Virtuoso Schematic Editor Window
• Delete the input voltages and the supply voltage
• Save Check
• Create -gt Cellview -gt From Cellview
• Click OK
• in Cellview From Cellview and Symbol
  Generation Options Windows