MPC555 Onchip IO Systems

1
MPC555 On-chip I/O Systems

• Part I Periodic Interrupt Timer, MPC555
  Interrupt Systems

2
Periodic Interrupt Timer

• Timer has many uses
• To implement a clock
• To check user input periodically
• To monitor environment changes
• To switch between programs

3
Periodic Interrupt Timer

• How does a timer work?
• A timer is basically a counter of clock cycles.

4
Periodic Interrupt Timer

• Time Period
• (count 1) clock cycle time
• (count 1) / clock frequency
• EX The clock frequency is 5MHz.
• The needed time period is 10ms.
• What is the count value?

5
Periodic Interrupt Timer

• EX The clock frequency is 5MHz.
• The needed time period is 1 second.
• The count register is 16-bit.
• What is the count value, and how to make it
  work?

6
Periodic Interrupt Timer

• How to program a timer?
• Set up count value
• Check if the timer expires
• Configure interrupt, if interrupt is to be used
• Read leftover value, if the can be supported

7
MPC555 PIT Programming

• PTE PIT enable PIF PIT freeze
• PITC PIT count value PS PIT status
• PIE PIT interrupt enable PITR leftover value in
  the counter

8
MPC555 PIT Programming

• MPC555 PIT programming interface
• PISCR Periodic Interrupt Status Control
  Register
• PITC PIT Counter
• PITR Periodic Interrupt Timer Register

9
MPC555 PIT Programming
PISCR Periodic Interrupt Status Control
Register
PInterrupt Enable 0 disable interrupt 1 enable
interrupt
0x002FC240
Interrupt levelfor PIT
1
2
3
4
5
6
7
0
PIRQ
PS
PIE
PITF
PTE
9
10
11
12
13
14
15
8
PIT Freeze 0 no effect 1 disable decrement
counter if internal signal FREEZE is asserted
PIT Enable 0 disable decrement counter 1
enable decrement counter
PIT Status 0 no PIT int asserted 1 PIT int
asserted
10
PITC PIT Counter
0x2F C244

• PIT Time-out period (PITC1)/(PIT Frequency)
• assume 1MHZ oscillator
• PIT Period 1/(1MHz) 1 microsecond
• Put 33000 in PITC to get 33 milliseconds
  interrupt
• period.

11
PITR Periodic Interrupt Timer Register
If you want to read the current PIT count to
estimate time to next PIT interrupt?
0x2F C248
16
31
15
0
Reserved
PIT
PIT Leftover (current) count in PIT
counter Writes to PITR have no effect read only.
12
PIT Initialization
.equ USIU_BASE_UPPER 0x2f .equ PICSR_OFFSET
0xc240 .equ PITC_OFFSET 0xc244 .equ PITR_OFFSET
0xc248 r4 base address of SIU regs lis r4,
USIU_BASE_UPPER set PICSR bits PIRQ08,
PSPS, PIE1, PITF0, PTE0 so OS flag is
cleared, interrupt is enabled, timer is
enabled, interrupt level is assigned, and device
disabled li r0,0x0800 sth r0,PICSR_OFFSET(r
4) PITC 33000 0x80e8 and store it in PITC
li r5, 0x80e8 sth r5, PITC_OFFSET(r4) now
enable PIT PTE 1 lhz r0,
PICSR_OFFET(r4) ori r0, r0, 0x1 sth
r0, PICSR_OFFSET(r4)
13
MPC555 Exception Processing
device 1
device 2
device n

External Interrupts
Interrupt controller
External interrupt exception
CPU
External Interrupt ESR
Other ESR
Other ESR
ISR 1
ISR 2
ISR n

14
MPC555 Exception Processing

• General Procedure of External Interrupt ESR
• Save machine context
• Make execution recoverable and enable external
  interrupt
• Save user registers
• Determine interrupt source
• Branch to ISR
• Restore user register contents
• Restore machine context
• Return to program execution

15
MPC555 Exception Processing

• What registers should be saved by CPU upon an
  exception?
• Should all registers be saved ALWAYS?
• Modern processors Software saves almost all
  registers
• But who should save the PC, CPU or software?

16
MPC555 Exception Processing

• Another register MSR (Machine State Register)
• User and supervisor modes An ESR runs in the
  supervisor mode
• Corresponding to the administrator privilege
• May access and change protected registers and
  memory areas
• How does the CPU switch to the supervisor mode?

17
MPC555 Exception Processing
18
MPC555 Exception Processing

• Upon an exception, the CPU
• Puts the ESR address into PC (forces a jump to
  the ESR)
• Change MSR bitsPR ? 0 Switches to supervisor
  mode (0 supervisor, 1 user)EE ? 0
  Disables further external interruptsRI ? 0
  Indicates not recoverable

19
MPC555 Exception Processing

• Key point ALL register values, if changed, must
  be saved and restored
• Include r0-r31, CR, LR, XER, PC, MSR and others
• ESR should save those register contents
• Can use stack
• But the CPU has changed the contents of PC and
  MSR!

20
MPC555 Exception Processing

• SRR0/SRR1 To save PC and MSR
• Solution Use special registers to help save them
• SRRx Machine status Save/Restore Registers
• SRR0 saves PC, SRR1 saves the changed bits in MSR
• How it works
• The CPU saves PC to SRR0, MSR to SRR1
• The ESR saves SRR0/SRR1 into stack

21
MPC555 Exception Processing

• Programming methods for saving SRR0/SRR1
• Example
• mfspr srr0, r3 copy srr0 to r3
• stw r3, 24(sp) save srr0 value
• lwz r3, 24(sp) get srr0 value in r3
• mtspr srr0, r3 copy it to srr0

22
Nested Interrupts

• If the interrupt ESR or an ISR is running, can
  the CPU accept another interrupt?
• Is it desirable to accept another interrupt?
• When cannot the CPU accept another exception?

23
Nested Interrupts

• EE bit Tell the CPU not to accept another
  interrupt
• External interrupt Enable bit
• Reset to zero The external interrupt exception
  is ignored the CPU keeps running
• The CPU automatically resets the EE bit upon an
  exception
• But the ESR may re-enable the EE bit

24
Recoverable Exceptions

• Other exceptions may happen during an interrupt
  processing
• Scenario Stack overflow during the interrupt
  processing
• Interrupt processing is not always recoverable
• Scenario The stack overflow happens before
  saving SRR0/SRR1
• Solution Use the RI bit
• The CPU automatically resets the RI bit
• The ESR may re-enable it