Computer Architecture Lecture 2

1
Computer ArchitectureLecture 2

• Abhinav Agarwal
• Veeramani V.

2
Quick Recap

• Various metrics in design of processor
• The interface internal structure
• Instruction Set Architecture
• Assembly instructions
• Instruction encoding

add r1, r2, r3
000111 00001 00010 00011
3
Outline

• RISC
• Multi-cycle execution
• Pipelining

4
Reduced Instruction Set Computer (RISC)

• Limited no. of instructions
• Fixed Length
• Simple to decode
• Easier to implement in hardware
• Prevalent in all commercial processors at the
  core level
• Counterpart C(omplex)ISC
• Intel processors
• Multi-operation instructions
• Still Intel processors have switched to RISC at
  second level

5
Execution Cycle of a RISC Instruction

• Five main phases of Instruction Lifecycle
• IF Instruction Fetch
• Read Instruction Memory at PC
• Bring the instruction into the CPU
• ID/RF Instruction Decode/Register Fetch
• Translate the opcode of the instruction to
  appropriate control signals
• No. of operands
• Registers clearly specified in instruction code
• Fetch operand values from the registers

6
Execution Cycle of a RISC Instruction

• EX ALU computation
• Activate appropriate functional unit Adder,
  Multiplier, Divider, Logical Unit
• Why no Subtracter?
• MEM Memory Operation
• Load/Store data from/to Data Memory
• WR Register Write
• Write the final result value into register

7
A Picture speaks a thousand words
8
Multi Cycle Execution

• Cycle Per Instruction (CPI)
• Kinds of Implementation
• One cycle for each stage
• Cycle time determined by longest stage
• CPI ?
• Combine all stages into a single cycle
• Cycle time determined by worst case instruction
• CPI 1

9
Execution Snapshot Cycle 1 IF
PC
00010
Address Instr
00000 Mov r2, 2A
00001 Mov r3, 12
00010 Add r1,r2,r3
00011 Store r1,0(r4)
00100 XXXX
00101 XXXX




10
Execution Snapshot Cycle 2 ID/RF
PC
Reg Data
r1 12 H
r2 2A H
r3 12 H
r4 00 H
r5 01 H





00011
Add r1, r2, r3
Address Instr
00000 Mov
00001 Mov
00010 add
00011 Store
00100 XXXX
00101 XXXX




11
Execution Snapshot Cycle 3 EX
PC
Reg Data
r1 12 H
r2 2A H
r3 12 H
r4 00 H
r5 01 H





00011
Add r1, r2, r3
Address Instr
00000 Mov
00001 Mov
00010 add
00011 Store
00100 XXXX
00101 XXXX




12
2A
Adder
12
Execution Snapshot Cycle 4 MEM
PC
Reg Data
r1 12 H
r2 2A H
r3 12 H
r4 00 H
r5 01 H





00011










Add r1, r2, r3
Address Instr
00000 Mov
00001 Mov
00010 add
00011 Store
00100 XXXX
00101 XXXX




12
2A
Adder
??
13
Execution Snapshot Cycle 5 WB
PC
Reg Data
r1 3C H
r2 2A H
r3 12 H
r4 00 H
r5 01 H





00011










Add r1, r2, r3
Address Instr
00000 Mov
00001 Mov
00010 add
00011 Store
00100 XXXX
00101 XXXX




Adder
14
Execution Snapshot Cycle 1 IF
PC
00011
store r1, 0(r4)
Address Instr
00000 Mov
00001 Mov
00010 add
00011 Store
00100 XXXX
00101 XXXX




15
Instruction Execution Timeline

• Sequential Execution
• Low utilization of functional units
• Alternative ?

store r1, 0(r4)
add r1, r2, r3
IF ID/RF EX MEM WB
IF ID/RF EX MEM
IF ID/RF EX MEM WB
Instruction Execution Timeline
16
Pipelining Concept and Example

• Washing machine, Dryer, Iron

source http//cse.stanford.edu/class/sophomore-co
llege/projects-00/risc/pipelining/
17
Pipelining Concept

• Remarkable Insight or Common Sense

Time Savings Per person 0 Overall 42
source http//cse.stanford.edu/class/sophomore-co
llege/projects-00/risc/pipelining/
18
Implementation of Pipelining in RISC

• Parallelism in all 5 stages
• New instruction every cycle
• Best case scenario

Inst
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
Time
19
Hardware Requirements
source http//cse.stanford.edu/class/sophomore-co
llege/projects-00/risc/pipelining/
20
Problems

• Data hazards
• Dependent Instructions
• add r1, r2, r3
• store r1, 0(r4)
• Control Hazards
• Branches resolution
• bnz r1, label
• add r1, r2, r3
• label sub r1, r2, r3
• Structural Hazards

IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
21
References

• Wikipedia CPU Parallelism http//en.wikipedia.org
  /wiki/Central_processing_unitParallelism
• http//www.cs.iastate.edu/prabhu/Tutorial/PIPELIN
  E/pipe_title.html