Multithreaded Processors

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Multithreaded Processors
Multi-Threaded Processor Architectures
The Tera MTA
Frank Casilio
Computer Engineering
May 15, 1997
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Problems with MultiProcessors

• Memory Latency

• Context Switching Time

• Communication/Synchronization Latency

• Poor Programming Model

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Motivation

• Reduce/Tolerate Memory Latency

• General Purpose Machine

• Scalability

• Shared Memory

• Simpler Programming Model

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Typical Ways To Reduce Latency

• Fast Buses Networks

• Hardware Synchronization

• Prefetching

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Multi-Threading The Concept

• Support For Multiple Concurrent Hardware Contexts

• Swap Contexts During Latencies

• Tolerates Latency Instead of Reducing It

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Parameters That Effect Efficiency

• Number Of Contexts Supported

• Switching Overhead

• Run Length (Granularity)

• Average Latency To Be Hidden

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Switching Theory

• Determines How Often Contexts Switch

• Directly Related to Cost

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Fine Grained Switching

• Switches Contexts Every Cycle

• Many Long Latencies Operations Tolerated

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Coarse Grained Switching

• Requires Less Contexts

• Requires More Complex Processors

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The TERA MTA

• First Commercial Multithreaded Machine Since 1978

• Uniform Shared Memory

• Fine Grained Architecture

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The Tera MTA Contd

• Torodial Interconnection

• 16-256 Processor Versions

• 12 Million Dollar Base System

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Processor Characteristics

• Support For 128 Threads

• 16 Protection Domains

• 0 Context Switching Overhead!!!

• 1 GFLOP Peak Performance

• 333 MHz Nominal Speed

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Processor Characteristics Contd

• 3 Operations Per Instruction

• 31 64-bit GPRs

• 6KW Of Power Dissipation Per Processor

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Interconnection Network

• 3-D Torus Contains 3p/2 nodes

• Packet Switching

• 3 Cycles of Latency Per Node

• Messages Are Assigned Random Priorities

• 2 HIPPI Channels / Processor For Net Connection

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Memory

• Either 2p or 4p Units, Interleaved 64 Ways

• 8, 16, 32 and 64 Bit Addressable

• 4 Bits per Word Of Access State For
  Synchronization

• Memory Units Equipped With Error Correcting Code

• Memory Usage In Random To All Banks

• 16 MB DRAM Chips

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Input / Output

• 20p MB/s In Each Direction

• At Least p/16 Disk Arrays Are Required

• System Capacity of 300p GB

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Operating System

• Allows Systems To Run p Tasks Truly Parallel

• Streams Are Dynamically Created w/o OS
  Intervention

• Processes Are Broken Up Into Tasks By OS

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Software / Languages

• Implicit And Explicit Parallelism Is Allowed

• High Degree of Cray Compatibility

• Easy To Program b/c Of Architecture

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System Performance

• 3.84-12.8 Times Performance Of Cray T90/32

• 1K x 1K Matrix Multiple in 50 ms

• Integer Sort of 100M Keys in 36 ms

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Conclusion

• Proven Effectiveness

• Logical Step For Multiprocessor Computers

• Still Very Pricey

• Allow General Purpose Workload

• Scalable

• Shared Memory

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Questions?
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Instruction Pipeline
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Breakdown Of A Task
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Deciding The Of Number Contexts