Red de sensores inalmbrica con comunicacin Bluetooth

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Review of DVS techniquesto reduce power
consumptionof digital circuits

S.C. Huerta, M. Vasic, A. de Castro, P. Alou,
J.A. Cobos Universidad Politécnica de
Madrid Escuela Técnica Superior de Ingenieros
Industriales División de Ingeniería
Electrónica http//www.upmdie.upm.es
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What does Integration mean?
ENGINEERING PROBLEM Thermal management, Energy
processing
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Efficient use of Energy
Optimize this!!
Toyota Prius
All the energycomes from the gasoline
Run the combustion engineat OPTIMUM operating
conditions
http//www.toyota.co.jp/en/tech/environment/hsd/04
.html
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DVS Dynamic Voltage Scaling
CMOS power consumption
V
V
Dynamic losses
dd
dd
Static
losses
Dynamic
losses
Dynamic
losses
EdynkCeqVdd2
V
th
C
C
L
L
Static losses
In 90 nm technologyleakage is already a problem
T. Pering, T. Burd and R. Brodersen, Voltage
Scheduling in the lpARM Microprocessor System
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DVS Dynamic Voltage Scaling

• Dynamic Voltage Scaling (DVS) allows a device to
  reduce energy consumption by lowering its
  processor speed at run-time, allowing a
  corresponding reduction in processor voltage and
  energy.

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Where is DVS implemented?

• Linux/RK ported to Compaq iPaq
• with support for frequency scaling3
• 206MHz StrongARM

• Portable devices (phones, PDA, laptops)
• Hardware accelerators1
• Systems On Chip2

• Linux running on voltage-scaling
• XScale board (ADIs BRH) prototype3
• 733 MHz XScale with 128MB DR1

Transmeta (DVD)
Fujitsu P2000 laptop with Transmetas Crusoe
1 M. Takahashi,"A 60-mW MPEG4 Video Codec Using
Clustered Voltage Scaling with Variable
Supply-Voltage Scheme". In IEEE Journal of
Solid-State Circuits, Vol. 33, No. 11, Nov
1998.2 F. Krisztián, F. David, R. Mark,A
Combined Hardware-Software Approach for Low-Power
SoCs Applying Adaptive Voltage Scaling and
Intelligent Energy Management Software,
DesignCon 2003, System-on-Chip and ASIC Design
Conference
3 Sukjae Cho, Power Management of iPAQ, USC
Information Sciences Institute
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Where is DVS implemented?
Power Savings
Processor and application
CPU bound application ,15 60 of power
savings, 5 20 degradation in performance
Intel Xscale, JPEG, GZIP, Qsort, floating- point
calculations, blowfish, CRC
memory bound application there was more than 70
of savings, 12 of performance degradation
30 80 , depending on the system utilization
Intel Xscale. Some RT applications
74 of savings, with 38 of average workload
Hitachi HI7750, MPEG
20 70, depending on complexity of the images
which are played
Simulation MPEG
20 50, of power savings
Simulations, MPEG-2, video phone applications,
avionics application
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Block diagram of DVS
INTEGRATION IS MANDATORY
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Block diagram of DVS
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Main blocks. Hardware (HW)
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Main blocks. Software (SW)

• Typical applications
• Multimedia applications (JPEG, MP3, MPEG
  encoders/decoders)
• Data manipulating applications (algorithms for
  data compression, searching, sorting,
  encryption/decryption)
• Other applications (FFT/IFFT, functions for
  producing cache misses/hits)
• Classification
• Memory bound
• CPU bound
• Depending on this, power savings may differ
  dramatically2

1 M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M.
Austin, T. Mudge, R.B. Brown, MiBench A free,
commercially representative embedded benchmark
suite, IEEE 4th Annual Workshop on Workload
Characterization, December 2001
2 K. Choi,R. Soma, M. Pedram, Fine-Grained
Dynamic Voltage and Frequency Scaling for Precise
Energy and Performance Tradeoff Based on the
ratio of Off-Chip Access to On-Chip Computation
Times, IEEE transactions on computer-aided
design of integrated circuits and systems
Jan.2005
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Main blocks. Software (SW)

• Power savings using DVS techniques range from 10
  to more than 70, depending on the necessary
  workload and type of application (CPU or memory
  bound)

K. Choi, R. Soma, M. Pedram,Fine-Grained Dynamic
Voltage and Frequency Scaling for Precise Energy
and Performance Tradeoff Based on the
Ratio of Off-Chip Access to On-Chip Computation
Times, IEEE transactions on computer-aided
design of integrated circuits and systems
Jan.2005
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Main blocks. Power Supply (PS)

• Convenient to be integratable

C
L
1 A. Soto, P. Alou, J.A. Cobos, J. Uceda, The
future DC-DC converter as an enabler of low
energy consumption systems with dynamic voltage
scaling, IECON 02 2 A. Soto, P. Alou, J.A.
Cobos, Design Methodology for Dynamic Voltage
Scaling in the Buck Converter, APEC 05.
Twentieth Annual IEEE, vol. 1, March 2005 3 A.
Soto, A. Castro, P. Alou, J.A. Cobos, J. Uceda,
A. Lotfi, Analysis of the Buck Converter for
Scaling the Supply Voltage of Digital Circuits,
APEC '03
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Main blocks. Power Supply (PS)

• The power supply needs to fulfill certain
  requirements1,2,3
• High efficiency over the whole voltage/power
  operating range
• Low tracking energy
• Fast output voltage transitions

1 A. Soto, P. Alou, J.A. Cobos, J. Uceda, The
future DC-DC converter as an enabler of low
energy consumption systems with dynamic voltage
scaling, IECON 02 2 A. Soto, P. Alou, J.A.
Cobos, Design Methodology for Dynamic Voltage
Scaling in the Buck Converter, APEC 05.
Twentieth Annual IEEE, vol. 1, March 2005 3 A.
Soto, A. Castro, P. Alou, J.A. Cobos, J. Uceda,
A. Lotfi, Analysis of the Buck Converter for
Scaling the Supply Voltage of Digital Circuits,
APEC '03
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Main blocks. DVS Schedulers

• Supervise the system and collect data in order to
  make appropriate decisions. Intelligence
• Type of Schedulers(according to their
  feasibility to be used in real time (RT) systems
• Schedulers not feasible for RT systems1,2
• Based on statistics - history algorithms
• Schedulers for RT systems. Take into account time
  constraints of each running task3,4,5

1 T.D. Burd, R.W. Brodersen, A.T. Pering, A.J.
Stratakos, A Dynamic Voltage Scaled
Microprocessor System, IEEE journal of
solid-state circuits Nov. 2000 2 K. Choi, R.
Soma, M. Pedram, Fine-Grained Dynamic Voltage
and Frequency Scaling for Precise Energy and
Performance Tradeoff Based on the Ratio of
Off-Chip Access to On-Chip Computation Times,
IEEE transactions on computer-aided design of
integrated circuits and systems Jan.2005 3 F.
Gruian,Energy-Efficient Scheduling for Hard RT
Applications on Dynamic Voltage Supply
Processors, 2003 4 S. Saewong, R. Rajkumar,
Practical Voltage-Scaling for Fixed-Priority
RT-Systems, Proc.of the 9th IEEE Real-Time and
Embedded Techn. and Applications Symposium
(RTAS03) 2003 IEEE, 2003 5 W. Kim, J. Kim, S.
Min, A DVS algorithm for dynamic-priority hard
real-time systems using slack time analysis,
Proceedings of the DATE'02, 2002
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Main blocks. DVS Schedulers

• The schedulers design needs to take into account
  that
• changing of voltage and frequency is not
  instantaneous
• frequency and voltage ranges are not continuous
• decreasing the dynamic consumption is not
  sufficient for the system (leakage and transition
  energy have influence)
• it is not necessarily advantageous to change
  voltage for every task

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Limitations
Dynamic Static losses
Voltage scaling of Vdd
Clustered Voltage scaling
Voltage scaling of Vth
1 W.M. Elgharbawy, M.A. Bayoumi, Leakage sources
and possible solutions in nanometer CMOS
technology, Circuits and Systems Magazine 2005 2
R. Jejurikar,C. Pereira, R. Gupta,Leakage aware
dynamic voltage scaling for RT embedded systems,
Proceedings of the Design Automation Conference,
2004.
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Limitations
Clustered voltage scaling
1 M. Takahashi, "A 60-mW MPEG4 Video Codec Using
Clustered Voltage Scaling with Variable
Supply-Voltage Scheme, IEEE Journal of
Solid-State Circuits, , Nov 1998
2 K. Usami , "Design methodology of ultra
low-power MPEG4 codec core exploiting voltage
scaling techniques," in Design Automation Conf.,
June 1998
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Limitations
VT-CMOS
Higher threshold voltage,for lower subtreshold
current 1,2
Lower threshold voltage,for high freq operation
1 W.M.Elgharbawy, M.A. Bayoumi, Leakage sources
and possible solutions in nanometer CMOS
technology, Circuits and Systems Magazine 2005
2 K. Usami, "Design methodology of ultra
low-power MPEG4 codec core exploiting voltage
scaling techniques," in Design Automation Conf.,
June 1998
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Limitations

• Clock Management Circuits
• How often the supply voltage can be changed
• Digital circuit is stopped during transitions
  (clock source)
• Slow transitions of power supplies and frequency
  management circuits (hundreds of us)
• PLL (Phase locked loop). Up to 1 ms to lock the
  desired frequency1
• DDL (Differential delay line). 8 clock periods to
  synchronize1

1 http//www.intel.com/design/intarch/papers/ddl48
6.htm
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Limitations

• Correlation between memory and processor1,2
• Optimize the complete energy consumption of
  memory bound applications
• In CPU bound applications it can be seen that
  memory consumption is almost only static power
  for RAM
• In Memory bound applications it is shown that
  power consumption of the memory can vary
  depending on the frequency

1 D. Snowdon, S. Ruocco, G. Heiser, Power
Management and DVS Myths and Facts, Proc. of
the 2005 Workshop on Power Aware RT Computing 2
X. Fan, C.S. Ellis, A.R. Lebeck, Synergy between
Power-aware Memory Systems and Processor Voltage
Scaling, Proceedings of PACS'03
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Research opportunities
FPGA
Maximal clock frequency vs. operating voltage
for FPGA chip Spartan 3
Power consumption vs. frequency for constant
voltage and minimal voltage of the core for FPGA
chip Spartan 3 (XC3s200)
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Research opportunities
Optimize the whole system

• Wide application rangeGeneral purpose, HW
  accelerators, embedded systems, SoC, sensor
  networks, networks on chip

• Appropriate algorithms
• History based
• µKernel

• Consider
• Dynamic static losses
• Time needed to change the clock (PLL, DDL, ,,,)
• Memory bound or CPU bound application

• Fast voltage transitions
• Low tracking energy
• Integratable

• From commercial µPto custom FPGA

for each specific application