Dr' Trevor Pearce

1
HLA to Simulate Computer Systems at the Hardware
Platform Level

• Dr. Trevor Pearce
• Amir Saghir
• Dr. Gabriel Wainer
•  
• Department of Systems and Computer Engineering
• Carleton University

2
Contents

• Motivation ? M S in product development
• Hardware Platform Framework
• DEVS
• Proposed Simulator
• Mapping to HLA
• Case Study

3
Motivation

• increase the use of M S in product development
• development of embedded applications
• real-time performance
• abstract models refine in development process
• hardware and software components
• at the hardware platform level ? but still
  abstract
• use DEVS for modelling
• broad applications, DEVS Standardization SG
• use HLA for simulation
• case study Intel 8088-based platform

4
General Approach

Application
Modelling Formalism
Simulator Engine
Middleware
Hardware
5
Specifics

6
HW Platforms
7
DEVS Atomic Model

• state machine
• state variables simulate using program
  variables
• transitions simulate using functions
• inputs trigger external transitions
• each state has a time advance ? autonomous
  activity
• internal transitions when time advance
  expires
• internal transitions can also generate outputs
• input before time advance?
• take external transition

8
Atomic Model (Visual)

input
?ext
Si tai
?int
output (?)
9
E.G. Memory Model
Triggered by input
Read control signal
along with the memory
d
location address
ext
Wait
Read
d
ta
taf(read)
µ

int
?
d
int
Triggered by
d
ext
Write control signal along
Triggered by
Write
with the memory location
the ta expire and carried
taf(write)
address and data
d
out before
int
10
DEVS Coupled Model

• connect inputs/outputs through ports
• creates hierarchy of models

Coupled Model
atomic or coupled
Model A
Model B
11
A Previous DEVS/HLA Simulator
12
Proposed DEVS Simulator
13
Mapping to HLA

• bus-related data ? shared data attributes
• coupling
• outputs ? published
• inputs ? subscribed
• time advance ? time advance request

14
Mapping to HLA (Visual)

input
receive reflect attribute
?ext
Si tai
?int
request time advance to current tai
send attribute update
receive time advance
15
Proposed Framework
16
Case Study

• simulator developed to verify the proposed
  approach
• simplified Intel 8088-based system
• model course-grained bus cycle activity
• single bus master
• software executing on simulated platform
• main program even number generator
• timer interrupt routine increments a counter
• verify behaviour using simulation logs
• compare instruction execution times to databook
  values
• accurate to clock cycle level

17
Future Extensions

• bus protocol models at signal level
• reuse module models
• introduce bus-level signaling module
• multiple bus masters (e.g. processor and DMA)
• multi-resolution simulation
• use course grain until bus conflict
• dynamic switch to clock cycle bus activity when
  needed

DONE !
module A
module B
semi-auto-generated from TDML spec of bus
protocols
bus model
bus model
RTI
18
Conclusions

• hardware platform modeling using DEVS
• simulation using HLA
• modeling details required for hardware components
• HLA-specific details
• attributes for input and output ports
• schedule time delays through RTI time management
• send outputs using RTI attribute updates
• atomic models only flattens DEVS hierarchy
• ? better performance results

19

• Thank you
• Questions ?