Implementation and Extensibility of an Analytic Placer

1
Implementation and Extensibility of an Analytic
Placer

• Andrew B. Kahng and Qinke Wang
• UCSD CSE Department
• abk, qiwang_at_cs.ucsd.edu
• Work partially supported by Cadence Design
  Systems, Inc., the California MICRO program, the
  MARCO Gigascale Silicon Research Center, NSF
  MIP-9901174 and the Semiconductor Research
  Corporation.

2
Motivation

• Automated placement always critical
• new challenges larger design sizes, shorter
  turnaround times, a variety of additional
  physical and geometrical constraints, etc.
• New analytical methods simultaneously spread
  cells and optimize wirelength
• force-directed placement Eisenmann et al. 98
• cell attracting and repelling (ARP) Etawil et
  al. 99
• Problem wirelength is easily damaged by improper
  forces and attractors

3
Our Contribution

• A novel objective function for spreading cells is
  proposed recently Naylor et al. 01
• We implement an analytic placer (APlace) based
  on this idea
• study characteristics of the objective function
• extend the objective function with congestion
  information
• implement a top-down multi-level placer WL
  outperforms that of QPlace, Dragon and Capo
• extend the placer to perform I/O-core
  co-placement for area-array I/O designs
• extend the placer with constraint handling for
  mixed-signal designs

4
Outline

• Problem Formulation
• Implementation Results
• Extensions
• Conclusion and Ongoing Work

5
Outline

• Problem Formulation
• cell spreading density control
• wirelength minimization
• Implementation Results
• Extensions
• Conclusion and Ongoing Work

6
Cell Spreading (I)

• Common strategy
• divide the placement area into grids
• equalize the total cell area in each grid
• Penalty of an uneven cell distribution
• not smooth or differentiable
• difficult to optimize

7
Cell Spreading (II)

• A bell-shaped cell potential function Naylor et
  al. US Patent 2001
• Cell c has potential(c, g) with respect to grid g
  
• Cell c at (CellX, CellY) has area A
• Grid point g (GridX, GridY)
• p(d) bell-shaped function
• r the radius of cells' potential
• C a proportionality factor, s.t.

8
Cell Spreading (III)

• Penalty function

EXPERIMENT Cell distribution results with
different number of grids and cell potential
radii (r's) for the ibm01-easy circuit.

• conjugate gradient solver
• stop when max movement of any cell between
  iterations is small
• Discrepancy(A)
• max ratio of actual total cell area to expected
  cell area over all windows with area A
• measure evenness of cell distribution
• disc Discrepancy(1 area)

9
Outline

• Problem Formulation
• cell spreading density control
• wirelength minimization
• Implementation Results
• Extensions
• Conclusion and Ongoing Work

10
Wirelength Formulation (I)

• Linear vs. quadratic objective functions
• Approximation of linear objectives
• precise
• continuously differentiable
• Previous works
• Gordian-L objective Sigl et al. 91
• a-order objective function Lillis et al. 95
• convex approximations of HPWL
• Alpert et al. 98 Baldick et al. 99 Kennings
  and Markov 00

11
Wirelength Formulation (II)

• Approximation of HPWL Naylor et al. 01
• log-sum-exp formula pick the most dominant terms
  among pin coordinates
• ? smoothing parameter

12
Wirelength Formulation (III)

• Experiments
• init HPWL 7.311
• 300 iterations
• a smaller ? wirelength formulation more accurate
  
• a larger ? WL minimized more quickly, and
  smaller final HPWL

EXPERIMENT Wirelength minimization results with
different smoothing parameters (a's) for the
ibm01-easy circuit.
13
Outline

• Problem Formulation
• Implementation Results
• Conjugate gradient optimizer
• Control factors
• Top-down hierarchical algorithm
• Placement results
• Extensions
• Conclusion and Ongoing Work

14
Conjugate Gradient Optimizer

• A series of line minimizations
• one-dimensional function minimization along some
  search direction
• gk the gradient ?f(xk)
• dk the search direction
• sk a step length obtained by a Golden Section
  search algorithm
• ?k ensures that dk is the conjugate direction
  when the function is quadratic and the line
  search finds the exact minimum along the
  direction
• Polak-Ribiere formula

15
Control Factors

• Weights of wirelength and density objectives
• density weight
• larger spread the cells out hastily without a
  good wirelength
• wirelength weight
• larger contract cells together and prevents them
  from spreading out

16
Control Factors

• Weights of wirelength and density objectives
• density weight fixed
• larger spread the cells out hastily without a
  good wirelength
• wirelength weight
• larger contract cells together and prevents them
  from spreading out
• set to be large in the beginning
• divided by 2 when the solver slows down and an
  optimal solution appears
• repeat until cells are spread evenly over the
  placement area
• grids
• coarser grids at the beginning spread out the
  cells faster
• finer grids at the final stages a more even
  distribution

17
Top-Down Multi-Level Algorithm

• A hierarchy of clusters
• MLPart Caldwell et al. 99
• Coarse grid average cluster size
• Density penalty
• regard each cluster as a macro cell
• area of the macro cell total area of the
  cluster
• Wirelength
• cells at center of clusters

18
Discrepancy and Wirelength
HPWL as a function of iterations for the
ibm01-easy circuit.
Discrepancy as a function of iterations for the
ibm01-easy circuit.
19
Placement Process

• Iter 100
• WL 4.06E5
• disc 10.69
• Iter 200
• WL 5.05E5
• disc 4.17
• Iter 300
• WL 4.04E5
• disc 2.53
• Iter 400
• WL 4.31E5
• disc 1.86

20
Legalization

• A simple Tetris legalization algorithm
• Hill 02
• sort cells according to vertical coordinates
• from left to right, search the current nearest
  available position for each cell
• fast
• increases WL by 5 on average for IBM-PLACE 2.0
  circuits
• Orientation optimization and row ironing
  UCLApack

21
Placement Results
Placement results of APlace for eight IBM-PLACE
2.0 circuits.
IBM-Place 2.0
Aplace 1.0
QPlace
Dragon
Capo
ckts
cells
nets
WL_l
WL_l
WL_l
WL
WL_l
disc
iter
CPU (m)
ibm01_easy
12282
11507
0.59
0.57
0.57
0.48
0.52
1.19
1098
12.6
ibm01_hard
12028
11507
0.56
0.55
0.56
0.46
0.50
1.18
1006
21.2
ibm02_easy
19321
18429
1.56
1.60
1.60
1.41
1.45
1.12
1097
30.3
19062
18429
ibm02_hard
1.52
1.47
1.56
1.38
1.44
1.11
1208
32.5
45135
44394
ibm07_easy
3.72
3.66
3.71
3.17
3.29
1.14
968
63.8
44811
44394
ibm07_hard
3.70
3.44
3.56
3.09
3.24
1.15
968
50.8
50977
47944
ibm08_easy
3.95
3.61
3.93
3.51
3.65
1.11
887
75.4
50672
47944
ibm08_hard
3.85
3.45
3.90
3.45
3.68
1.11
806
55.3

• Comparison (HPWL)
• Cadence QPlace (SE5.4) 9.0 (4.5 12.7)
• UCLA Dragon (2002) 4.8 (-6.5 10.2)
• Capo (v8.7) 8.7 (5.7 11.4)
• Comparison (Running Time)
• Xeon server (2.4GHz CPU, double-threaded)
• faster than Dragon (0.8X), much slower than Capo
  (13.2X)

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Outline

• Problem Formulation
• Implementation Results
• Extensions
• Congestion-directed placement
• IO-core co-placement
• Constraint handling
• Conclusion and Ongoing Work

23
Congestion-Directed Placement (I)

• Accurate bend-based congestion estimator Kahng
  and Xu, SLIP-03
• Congestion-directed placement
• ExpPotential(g)
• expected total potential at grid point g
• reduced, if g is congested
• ? congestion adjustment factor

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Congestion-Directed Placement (II)

• Experiments
• routability
• WL in gcell grid
• over-capacity gcells
• routability 38 better with ? 0.05
• routability deteriorates with larger ?

Placement and global routing results with varying
congestion adjustment factors (? 's) for the
ibm01-hard circuit.
25
Experimental Results
Placement and routing results of APlace for eight
IBM-PLACE 2.0 circuits with comparison to QPlace,
Dragon and Capo.

• Comparison (Routed WL)
• Cadence QPlace (SE5.4) 8.2
• UCLA Dragon (2002) 4.2
• Capo (v8.7) 10.4
• With orientation optimization and row ironing
• Cadence QPlace (SE5.4) 12.0
• UCLA Dragon (2002) 8.1
• Capo (v8.7) 14.1

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I/O-Core Co-Placement

• Peripheral I/O
• constrained clock/power distribution
• coupling and power issues for off-chip signaling
• Area-array I/O
• improved pad count and reliability
• reduced noise coupling
• Simultaneous I/O and core placement
• I/Os are spread over the placement area, in the
  same way and at the same time as core cells
• DensityWeight DensityPenalty IODensityWeight
  IODensityPenalty

27
I/O-Core Co-Placement Results
I/O-core co-placement results with different
number of I/Os.
I/O-core co-placement with 400 I/Os for
ibm01-easy circuit.

• Randomly select 400 or 1000 cells and regard them
  as I/Os
• I/Os distributed fairly evenly
• WL, disc of core cell distribution, and running
  times not seriously impaired

28
Placement with Geometric Constraints

• Mixed-signal ASIC designs parasitic effects
• a large number of constraints
• Constraints in APlace convert to penalty
  functions
• alignment constraint, e.g.
• spacing constraint, e.g.
• axial symmetry, e.g.
• nodal symmetry, e.g.

29
Constraint Handling Results
Placement of APlace with 90 artificial geometric
constraints for ibm01-easy circuit.
Placement results of APlace with 90 artificial
geometric constraints.

• Average WL increase 8.2
• Blue Alignments
• Red Nodal Symmetries Spacing
• Black Axial Symmetries Spacing

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Conclusion and Ongoing Work

• Implemented and conducted in-depth analysis of
  characteristics and results of APlace
• placed and routed wirelengths outperform QPlace,
  Capo and Dragon.
• Extended the basic formulation
• top-down hierarchical placement,
  congestion-directed placement, I/O-core
  co-placement, and constraint handling
• Ongoing work
• timing-driven placement
• mixed-size placement

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Prof. C.-K. Cheng, UCSDBo Yao, UCSDProf. Igor
Markov, MichiganSaurabh Adya, MichiganShubhyant
Chaturvedi, MichiganProf. C.-K. Koh, PurdueChen
Li, PurdueProf. Andrew Kennings, Waterloo
Thanks
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Thank You !