HBM 3D-stacked DRAM technology

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HBM 3D-stacked DRAM Technology

• OpenFive offers HBM2/2E IP Subsystem for High-end
  graphics, high performance computing, high end
  networking high end communications and 2.5D and
  3D ASIC design.
• HBM2/2E IP Subsystem
• The HBM2/2E IP is suitable for applications
  involving graphics, high-performance computing,
  high-end networking, and communications that
  require very high bandwidth, lower latency and
  more density.
• HBM2/2E IP SPECIFICATIONS
• Key Features
• Integrated HBM controller and HBM PHY subsystem
  solution supporting HBM2 and HBM2E JEDEC spec for
  a wide range of technology and foundry nodes.
• As an early advocate of 2.5D and 3D ASIC design
  technologies and by leveraging its experience
  from the industrys first multiple successful
  2.5D SoC SiP demonstration, Open Five plays a key
  role in enabling industry applications that
  leverage the HBM 3D-stacked DRAM technology.

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HBM2/2E IP Subsystem

• OpenFive is a solution-centric silicon company
  that is uniquely positioned to design processor
  agnostic SoC architecture. With customizable and
  differentiated IP,
• OpenFive develops domain-specific SoC
  architecture based on high-performance,
  highly-efficient, cost-optimized IP to deliver
  scalable, optimized, differentiated silicon.
  OpenFive offers end-to-end expertise in
  Architecture, Design Implementation, Software,
  Silicon Validation and Manufacturing to deliver
  high-quality silicon.
• The HBM memory specification is alive and well
  with new, high performance versions available
  today and more in the pipeline.
• If youre still on the fence about attending,
  here is some information that should help. The
  event will cover three aspects of HBM-based
  designs
• Ketan Mehta, Director, SoC IP Product Marketing
  at SiFive will cover markets, applications and
  roadmaps
• Pranav Kale, Staff Engineer, SoC IP Engineering
  at SiFive will cover the features of the new
  HBM2/2E standards

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HBM2/2E ASIC SiP (System in Package)

• Protocol controller
• JEDEC (JESD235B) HBM2/2E DRAM specification
  compliant
• Pseudo-channel mode support
• Multi stack HBM2/2E memory support
• Power down self-refresh modes
• Low latency controller features
• Per channel data rate Up to 3.2Gbps/pin
• Configurable independent channels
• Memory access optimizations for bandwidth
  efficiency
• Configurable error injection mechanisms for
  testability
• DFI-like controller/PHY interface
• Supports 11 21 PHY/controller frequency
  ratios
• Memory die diagnostic features
• JTAG connectivity for IEEE-1500 access, lane
  repair, training and loopback test modes
• Multiple in-built test diagnostic features

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PHY Layer

• Ultra-low latency
• Easily portable across technologies
• Includes I/O, PLL DLL
• Coarse and fine grain I/O training
• Low-power HBM memory and PHY modes
• Complies to ESD requirements
• Loopback support for testability
• JEDEC (JESD235B) HBM2/2E DRAM specification
  compliant
• Optional support for LLHBM
• Process node supports TSMC16/12nm, TSMC7nm,
  GF14/12nm, GF22FDx

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Die-to-Die Interposer I/O

• CMOS I/O with programmable drive strengths
• 3.2 Gbps / 1.6 GHz DDR with light output loading
• Up to 5mm interposer trace length support meeting
  gt 3.2 Gbps per pin date rate
• Electrically compatible with JEDEC HBM2/2E spec
• Low latency controller features
• Optional differential receiver

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• Please do visit my website for
• in-depth information.
• Website https//openfive.com/
• HBM 3D-stacked DRAM technology
  https//openfive.com/hbm2-2e-ip-subsystem/