SWITCH-MODE POWER SUPPLIES AND SYSTEMS

1
SWITCH-MODE POWER SUPPLIES AND SYSTEMS
Lecture No 6

• Silesian University of Technology
• Faculty of Automatic Control, Electronics
• and Computer Sciences
• Ryszard Siurek Ph.D., El. Eng.

2
Switch-Mode Power Converters
Application of the switching transformer -
ensures galvanic isolationbetween output and
input circuit (safety regulations, output
voltage polarity not restricted) - small
transformer dimensions according to high
switching frequency - output voltage higher or
lower than the input voltage independently of
switching regulator configuration -
possibility of efficient operation (with optimum
duty cycle) in presence of high difference
between input and output voltage (mains input
voltage - very low output voltage) - several
output voltages easily available
3
Single-ended forward converter
typical step-down regulator output filter
Ip
T
D2
L
IS
Up
UIN
Uw
t
T
D1
C
R0
Zp
ZS
U0
CIN
Za
turns ratio
Transformer model
ideal transformer

rp
Llp
Lls
Ip
Iw Iw /n
IS
FM
Lp

Up
US
Up USn
IM
n
Assumptions Llp, Lls 0
rp, rs 0
4
Forward converter equivalent circuit
I cycle 0 lt t lt t transistor T - ON
, diode D2 - ON, diode D1 - OFF
L
T
Ip IT
IS
IL
D2
Up
US
FM
R0
U0
UIN
IM
C
D1
Lp
IM
n
IT
IT
IMmax
IM
IMmax
t
IL
ILmax
ILmin
FM
FMmax
5

II cycle t lt t lt T Transistor T -
OFF , diode D2 - OFF, diode D1 - ON
Da
L
IS0
IL
T
Ip 0
dUp
Zp
D2
dUa
FM
UT
dUS
IM
R0
U0
UIN
Za
C
D1
Lp
Up
UaUIN
n
IM
USUp/n
IT
Up
IT
IMmax

1. When T switches off the overvoltage dUp appears
   across Zp and is transformed as dUS to the
   secondary side
2. Diode D2 switches off , overvoltage is
   transformed to the winding Za and diode Da
   switches on
3. The voltage Ua acrosss Za approaches the value of
   UIN and can not rise any more
4. Voltage UaUIN is transformed to the primary
   winding Zp and is limited on the value Up
5. The core of the transformer is being demagnetised
   during t1 (core reset)

IM
IMmax
t
T
ILmax
IL
I0
ILmin
FM
IM
FMmax
current in Za
current in Zp
IMmax
t
t1
UT
UIN
6
Transformer core reset (magnetizing energy
recovery) detailed analysis
UT
dULL
UT
iZa(t)
iZp(t)
real overvoltage
T
UIN
LL
dULL
UIN
t1
UIN
Lp
t
T
Zs
IZp
IMmax
Zp
Za
To keep dULL low, LL should be small
enough - it requires very good magnetic
coupling between the windings Zp and Za In
practice Zp Za and both windings are
bifilary wound hence UTmax 2UIN
IZa
FM
FMmax
Full demagnetization of the transformer is
possible under the following condition
7
Typical magnetizing energy recovery circuits

Da
ZpZa
D2
L
D1
C
R0
Zp
ZS
U0
CIN
Za
UIN
Cs
overvoltage dumping circuit - snubbar circuit
T
Rs
Ds
Disadvantages necessity of placing two bifilar
windings , difficult construction, high
transformer cost, problems with insulation, duty
cycle limited to g lt 0,5, snubbar circuit
required to avoid voltage stress across the
switching transistor Advantages most of
transformer magnetizing energy is recovered
(higher efficiency), only one switching
transistor, simple transistor gate drive circuit
8
D2
L
Rs
Cs
D1
C
R0
Zp
ZS
U0
Up
UIN
CIN
When Uo rises (higher value of Rs), core reset
time t1 decreases and may be shorter than t. That
is why the duty cycle may be higher (g
gt 0,5)
T
UTUpUIN
Disadvantages magnetising energy is dissipated
in Rs, lower efficiency, high power resistor
(resistors) are required, heating of some
components, high coltage stress across the
tswitching transistor ( UT gt 2UIN) Advantages s
imple and cheap transformer, duty cycle not
limited to 0,5, no extra voltage spikes across
the transistor no influence of leakage
inductance This configuration
is not used in practice due to excesive power
losses
9
T1
D1
D2
L
Ip
US
Up
D1
C
R0
Zp
ZS
U0
UIN
CIN
T2
UpUIN g lt 0,5
D2
Disadvantages two switching components,
complicated drive circuits, higher
cost Advantages simple transformer, no
excesive voltage spikes problem of leakage
inductance does not exist, transistor voltahe
does not exceed UIN This configuration often used
in power supplies with higher output power
usually over 300 500W
10
Magnetic core behaviour, magnetising curve ,core
saturation
B
B
Bs
Bs
H
H
Core saturation in case of improper transformer
design
-Bs
-Bs
iM(t)
Ip
FM
IM
demagnetising current
FM
FMmax
magnetising current

iS(t)
IM
IMmax
t
t
t
t1
11
Core saturation as a result of incomplete core
reset (transformer demagnetisation)
FM
B
Bs
t
H
Ip
t
-Bs
12
Output choke (inductance) saturation
B
IL
Bs
I1
DB
B0
I0
t
DH
H
H0(I0)
H1(I1)
Ip
-Bs
t