PicoNode II Implementation

1
PicoNode II Implementation

• Friday Lunch Presentation
• 26 January 2001
• Mike Sheets

2
Overview

• System Architecture
• Implementation
• Baseband hardware path
• Protocol hardware path
• Protocol software path
• Status

3
System Overview
Remote 2
Remote 1
channel
Basestation
Intercom style communication multiple remotes
can participate in the same conference
4
High Level Architecture
ADC
Digital Baseband Processing
Analog RF
DAC
Protocol
Baseband
RF front-end
Can be easily merged into a single chip, but
separate now to remove implementation dependencies
5
Node Architecture

Cache
FPGA
SRAM
InterfaceController
Dedicated HW
Flash Controller
Xtensa uP
Flash
Silicon Backplane
Baseband Datapath
PowerAmplifier
D/A
6
Physical Layer

• Application Intercom-style voice conversations
• 15-20 users, 64Kb/s/user
• Requires up and downlink, peer-to-peer PHY
• Provide simple interface to protocol stack

• Existing RF, analog components support
• 31 chips/symbol DSSS
• 25 MHz chip rate
• QPSK mod
• Supports 1.6Mb/s
• TDMA supports required bandwidth, user count

• Leverage existing analog, RF components.

7
Baseband Algorithm

• Input 8 pre-interpolated data streams from ADC
• Coarse timing and code acquisition
• feed forward, non-data-aided algorithm based on a
  matched filter
• Joint carrier offset and fine timing
• feedforward and data-aided synthesized directly
  from ML equations
• Phase estimation using phase-locked loop (PLL)
• Data-aided acquisition using known pilot symbols
  to estimate phase offset
• Decision-directed data reception using detected
  symbols to calculate error

8
Baseband Models

• Dataflow blocks
• Structural models in Simulink with corresponding
  Module Compiler blocks
• Control blocks
• Structural models in Stateflow

Stateflow example Receiver controller
Simulink example Matched filter correlator
9
Physical Layer Design Flow
10
Baseband Floorplan
Chip floorplanestimated die area 2.2 mm2

• Nominal clock rate is 25 MHz
• Estimated power consumption
• Carrier search mode 7.6 mW
• Acquisition mode 0.47 mW
• Data reception 1 mW

11
Protocol Chip

• System-On-Chip design with cores and synthesized
  interconnect
• Entry language is Verilog
• Protocol core 65 hand-written modules
• Xtensa core generated by Tensilica
• Other cores 5 handwritten modules
• Interconnect/interfaces 15 generated modules
• Memories
• Black boxes generated by ST

12
General Block Design Flow
Synopsys DesignCompiler Ambit BuildGates
Synthesis
Verilog (.v)
Structural netlist
Timing constraints
Cadence SiliconEnsemble
Floorplan
Technology library
Placement
Cadence SiliconEnsemble
Clock tree
Cadence CTGen
Routing
Cadence WarpRoute
Timing closure
Extraction
Cadence HyperExtract Arcadia
Verification
Cadence SiliconEnsemble, Cadence Dracula, etc.
Final design
13
Cadence SPR Flow
Synthesis/Floorplanning Physical Knowledgeable
Synthesis, automatic floorplanning, area
estimation, and timing-driven block
placement Floorplanning refinement Block
refinement and power routing
PKS
SiliconEnsemble/DesignPlanner
Placement, Special Nets, and Optimization Timing-d
riven placement, clock tree generation, scan
re-ordering, and post-placement
optimization Global Routing and
Optimization Timing-driven global routing and
post-route optimization
PKS (CTPKS)
Final Routing
WRoute
Parasitic Extraction
HyperExtract
In-Place Optimization SPF backannotation and
timing correction
PKS
Verification Verify geometry and connectivity
SiliconEnsemble
14
ST Unicad Flow

• Similar to Cadence flow
• Entry point is after synthesis (structural
  netlist)
• Same basic tools SiliconEnsemble, CTGen,
  WarpRoute, etc.
• Set of scripts that interface tools
• Custom tailored to specific versions of the tools
• Requires an experienced user to handle things
  that break the scripts
• Tool integration
• Not as tight as Cadence flow so incremental
  changes are harder (timing closure)
• ST is our foundry so Unicad works well with their
  libraries

15
VCC SW Code Generation

• void cyg_user_start(void )
• cyg_thread_create(0, task_ui_2_, 0, )
• cyg_thread_create(0, task_transport_1_transport_b
  s)
• cyg_thread_create(0,task_transport_1_transport_re
  mote_,)
• cyg_thread_create(0, task_transport_1_merge2_,
  0, "T3",)
• cyg_thread_create(0, task_transport_1_data_conver
  ter_, 0, ..)
• cyg_thread_create(0, task_transport_1_merge1_,
  0, "T5", )
• cyg_thread_resume(task_ui_2__handle)
• cyg_thread_resume(task_transport_1_transport_bs__
  handle)
• cyg_thread_resume(task_transport_1_transport_remo
  te__handle)
• cyg_thread_resume(task_transport_1_merge2__handle
  )
• cyg_thread_resume(task_transport_1_data_converter
  __handle)
• cyg_thread_resume(task_transport_1_merge1__handle
  )

• Programming model in the exported code is that of
  a traditional OS.
• Each Instance is turned into a task. Task
  management relies on the OS.

16
Using a Traditional OS

• Power / Performance
• Complicated data structures and too much overhead
  associated with traditional OS (memory
  allocation, context switching etc).
• Code size blows up application codegt 30K
• Programming model does not match the underlining
  model for the application (EFSM).
• Many macros functions.
• For each instance LockEvents(), ClearEvents(),
  init(), run()
• For each input port (pin) Enable(), Value (),
  valueP (),
• For each output pin SetPresence(), BuffWrite()
  and Post(),
• Other macros for communication buffers,
  synchronization etc.
• No power management

17
Potential Solution

• A programming model more suitable for protocol
  processing.
• Reactive event-based operating environment
• Supports concurrency intensive operations.
• Highly efficient resource utilization (memory,
  energy etc).
• No wasteful polling and context switching
• Aggressive power management.

18
Implementation Status

• Baseband
• Simulink simulation is almost complete
• ModuleCompiler blocks are drafted
• SSHAFT flow has been successfully tested on one
  of the blocks
• Protocol hardware
• Physical design is underway goal March 1, 2001
• Proceeding with Unicad 2.4 flow (future design
  with SPR flow)
• Protocol software
• Software exported from VCC
• Operating system nearly complete

19
Implementation Team

• Baseband
• Josie Ammer, Mike Sheets
• Rhett and the entire SSHAFT team
• Protocol hardware
• Julio Silva, Mike Sheets, Huifang Qin
• Qian Yu, Jeffrey Tsai
• Protocol software
• Suet-Fei Li