Lecture 24: Review

1
Lecture 24 Review

• Presentations on Tuesday work in pairs, 5-6
  slides each.
• If your circuit is already working, demonstrate
  it after class.
• If you need more time, I will be in the lab from
  11am 12 on the morning of the exam (Dec 16th)
  or arrange another time before then with me.
• Anthonys Birthday!!!!
• Exam preparation use assignments, go over the
  mid-term.
• Cant review everything focus on some older
  stuff today
• Simple circuits equi valent circuits (work for
  both AC DC)
• KCL KVL mesh or nodal analysis. Works for AC
  DC
• Thevenin Norton circuits
• Transient circuits capacitors inductors
• These notes contain more, and will be posted on
  the web

2
Assignment 9 solutions
Design a 3-bit binary up-counter using D-FF to
cycle over all odd numbers. To optimize the
design, you are allowed to reset any even number
states into any one of these odd numbers. At the
end, show the complete state diagram with even
numbered states, indicating which odd number they
reset to. (Hint your final design should
contain 3 D-type flipflops and a single
combinational logic gate)
3
Assignment 9 solutions
Design a 3-bit binary up-counter using D-FF to
cycle over all odd numbers. To optimize the
design, you are allowed to reset any even number
states into any one of these odd numbers. At the
end, show the complete state diagram with even
numbered states, indicating which odd number they
reset to. (Hint your final design should
contain 3 D-type flipflops and a single
combinational logic gate)
4
Assignment 9 solutions
1) Design a 2 bit counter counting 0, 1, 2 using
D-FF. There are two inputs a data input which
receives clock pulses, and a count direction
input which when HIGH causes counting up and when
LOW causes counting down. You may treat the
excluded state 3 as you see fit to simply your
design. At the end, indicate where the state 3
goes into
5
Assignment 9 solutions
1) Design a 2 bit counter counting 0, 1, 2 using
D-FF. There are two inputs a data input which
receives clock pulses, and a count direction
input which when HIGH causes counting up and when
LOW causes counting down. You may treat the
excluded state 3 as you see fit to simply your
design. At the end, indicate where the state 3
goes into
6
Assignment 9 solutions
1) Design a 2 bit counter counting 0, 1, 2 using
D-FF. There are two inputs a data input which
receives clock pulses, and a count direction
input which when HIGH causes counting up and when
LOW causes counting down. You may treat the
excluded state 3 as you see fit to simply your
design. At the end, indicate where the state 3
goes into
7
Simple circuits

• Voltage/Current sources provide prescribed
  voltage/current regardless of load
• Kirchoff's current law The sum of currents into
  a node0
• Kirchoff's Voltage Law The sum of voltages
  round a closed loop0
• Voltage divider
• Current divider

8
Circuit analysis method 1Apply element
combination rules
Series resistors
Parallel resistors
Series voltage sources
Parallel current sources
9
Mesh Analysis

• Example 2 meshes
• (Mesh is a loop that does not contain other
  loops)
• Step 1 Assign mesh currents clockwise
• Step 2 Apply KVL to each mesh
• The self-resistance is the effective resistance
  of the resistors in series within a mesh. The
  mutual resistance is the resistance that the mesh
  has in common with the neighbouring mesh
• To write the mesh equation, evaluate the
  self-resistance, then multiply by the mesh
  current
• Next, subtract the mutual resistance multiplied
  by the current in the neighbouring mesh for each
  neighbour.
• Equate the above result to the driving voltage
  taken to be positive if it tends to push current
  in the same direction as the assigned mesh current

Mesh1 (R1R2)I1 - R2I2 e1-e2
Mesh2 -R2I1 (R2R3)I2 e2-e3
Step 3 solve currents use substitution or
Cramer's rule
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Cramer's Rule
Step 3 solve currents use substitution or
Cramer's rule
I - I2 - I3 0
4I 5I2 0I3 3
0I - 5I2 10I3 0
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Mesh Analysis with 3 loops
12
Mesh analysis with a current source
Magnitude of current in mesh containing current
source is IS , (although if the current flow is
opposite to the assigned current direction the
value will be negative).
This works only if the current source is not
shared by any other mesh For a shared current
source, label it with an unknown voltage.
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Example

• In this circuit, find the value of Is that will
  reduce the voltage across the 4O resistor to zero.

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Example

• In this circuit, find the value of Is that will
  reduce the voltage across the 4O resistor to zero.

Mesh equation
when 4O voltage0

• What if the 2 O and the 6 O resistors are
  swapped?

15
Example II

• Which of the two circuits has the larger
  terminal voltage, A or B?
• Which has the larger current through the 9V
  battery?
• Practical batteries are modelled as voltage
  sources in series with a resistor.

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Example II

• Which of the two circuits has the larger
  terminal voltage, A or B?
• Which has the larger current through the 9V
  battery?
• Practical batteries are modelled as voltage
  sources in series with a resistor.

Mesh equations
Mesh equations
i1 current through battery solve to give i10.41A
i1 current through battery solve to give i1
-0.56A
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Example II

• Which of the two circuits has the larger
  terminal voltage, A or B?
• Which has the larger current through the 9V
  battery?
• Practical batteries are modelled as voltage
  sources in series with a resistor.

VR
-
-
i1
-
i1
-
VR


-
-
i1 current through battery solve to give i10.41A
i1 current through battery solve to give i1
-0.56A
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Thevenin and Norton Equivalent Circuits
Any network of sources and resistors will appear
to the circuit connected to it as a single
voltage source and a series resistance
load
vTH open circuit voltage at terminal (a.k.a.
port) RTH Resistance of the network as seen
from port (Vms, Ins set to zero)
load
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Thevenin and Norton Equivalent Circuits
Any network of sources and resistors will appear
to the circuit connected to it as a single
current source and a parallel resistance
How do we calculate RT, VT, iN, RN ?
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Calculation of RT and RN

• RTRN same calculation
• Set all sources to zero (kill the sources)
• Short voltage sources
• Open Current sources

• Calculate equivalent resistance seen by the load

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Calculation of VT

• Remove the load and calculate the open circuit
  voltage

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Example

• Find the Thevenin equivalent

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Example

• Find the Thevenin equivalent

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Example

• Find the Thevenin equivalent

Y
X
X
Y
25
AC circuit elements

• Capacitors in series

• Capacitors in parallel

• Capacitive impedance ZC1/j?C

• Inductors in series

• Inductors in parallel

• Inductive impedance ZL j?L
• Circuit analysis tools for DC circuits work on
  AC circuits, but replace resistance with impedance

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AC circuit analysis example
If V110cos(1000t) (volts) and V25cos(1000t)
(volts), what is the current through the
capacitor?
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AC circuit analysis example
If V110cos(1000t) (volts) and V25cos(1000t)
(volts), what is the current through the
capacitor? Mesh 1 (100ZC)I1-ZCI2V1 Mesh 2
-ZcI1(ZcZL)I2-V2
IC(j?)I1(j?)-I2(j?)0.05j0.050.05j0.050.1j f
tan-1(0.1/0.05) 63 degrees Av(0.0520.12)0.11
IC(j?)0.11?63 iC(t)0.11cos(1000t63)
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Charging a capacitor
Time constant tRC. Time needed to charge
capacitor to 63 of full charge Larger RC means
the capacitor takes longer to charge Larger R
implies smaller current flow The larger C is, the
more charge the capacitor can hold.
Solution is only true for simple circuit with
resistor and capacitor in series, but more
complicated circuits can be reduced to this using
Thevenin's Theorem
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Example
A battery with an emf of 1.5V and an internal
resistance of 0.6O is used to charge a 5F
capacitor when a switch is closed. How long does
it take to reach a voltage across the capacitor
of 1V?
5F
30
Example
A battery with an emf of 1.5V and an internal
resistance of 0.6O is used to charge a 5F
capacitor when a switch is closed. How long does
it take to reach a voltage across the capacitor
of 1V?
5F
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Example
How long does it take if we attach an additional
battery with an emf of 9V and an internal
resistance of 18O as shown?
5F
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Example
How long does it take if we attach an additional
battery with an emf of 9V and an internal
resistance of 18O as shown?
RTH0.58 i0.40A VTH1.74
5F
Time to 1V 2.5 seconds
5F
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Op Amps
Remember the Golden Rules 1) iin0 no current
flows into the opamp. 2) vv- These are only
valid when there is negative feedback In many
circuits, one input to the opamp is connected to
ground, so vv-0
A simple example
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Op Amp circuits
Summing Amplifier
Inverting Amplifier
Non-Inverting Amplifier
Differential Amplifier
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Integrator
Differentiator
And two without negative feedback
Schmitt Trigger
Comparator
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Example
What does this circuit do? Derive an expression
for the gain and give the circuit a suitable name.
i2
R2
i1
R1
R1
R1R2
R2
voltage divider
37
Example
Design an opamp circuit to convert the triangular
waveform v1 in the following figure into the
square wave v0 shown. Use a 0.1µF capacitor.
(Hint first quantitatively determine the
mathematical expression of v0 in terms of v1)
v0 is v1 differentiated
38
Simple Filter analysis Which of the following is
a low-pass filter?

• What happens to the output voltage when ??0 (DC
  condition)?
• In DC circuits, capacitors are open, inductors
  are shorts.
• or when ??8
• At very high frequencies, capacitors are shorts,
  inductors are open

Answer (c)
39
For a more quantitative solution, find the
complex transfer function

• RC low-pass filter preserves lower
  frequencies, attenuates frequencies above the 3dB
  cutoff frequency ?01/RC.

(For voltage)
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Example
Design a high-pass RC filter with a 3dB frequency
cutoff of 80Hz using a capacitor of 2µF
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Active Filters
42
Example
Given an input signal Vi10mV(sin10tsin10,000t),
design a circuit such that the output signal is
VO -100mV(sin10t). The high frequency component
of the output signal must be frequency part. So, we want a circuit which
amplifies the voltage, but only at low
frequencies need an active filter.
43
Example
Given an input signal Vi10mV(sin10tsin10,000t),
design a circuit such that the output signal is
VO -100mV(sin10t). The high frequency component
of the output signal must be frequency part. So, we want a circuit which
amplifies the voltage, but only at low
frequencies need an active filter.
Low frequency ?1 Want a gain of 10 ?1RFCFso set RS1kO set RF10kO
High frequency ?2 Low frequency gain10, so for
Check low frequency
44
Combinational logic design steps

• Derive the Truth Table
• Fill the Karnaugh map
• Use the map to find the logic
• Implement the logic in a circuit

45
Another Example 7 segment displays
Karnaugh Map for "a"
Truth Table
"x" represents a "don't care" condition - the
value can be either 0 or 1
46

• Box the ones for sum-of-products

• This subcube B

This subcube AC
This subcube A'C'
This subcube D
47

• Realization (sum-of-products) is BD AC A'C'

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Sequential logic design steps

• List the states - assign each state a symbol
• Draw the finite state diagram (Moore - states
  inside nodes)
• Derive the symbolic state transition table
• Assign each state a binary code (also each
  output, if more than one)
• Derive the actual state transition table
• Write out the Karnaugh map for each "next state"
  and output(s)
• Solve the maps to find the logic
• Implement the logic in a circuit

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3-bit binary up-counter
List the states 0 to 7
Derive the symbolic transition table
Draw the finite state diagram
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Derive the actual state transition table
Assign the states a binary code
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Derive the actual state transition table
current
next
Solve the maps
notation to show function representing input to
D-FF
N1 C1' N2 C1C2' C1'C2 C1 xor C2 N3
C1C2C3' C1'C3 C2'C3 C1C2C3' (C1'
C2')C3 C1C2C3' (C1C2)'C3 (C1C2)
xor C3
Karnaugh maps for each "next state"
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Implement the logic each state bit requires one
memory element (flipflop)
current
next
N1 C1' N2 C1C2' C1'C2 C1 xor C2 N3
C1C2C3' C1'C3 C2'C3 C1C2C3' (C1'
C2')C3 (C1C2) xor C3