Very High Radix Scalable Montgomery Multiplication

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Very High Radix Scalable Montgomery Multiplication

• Kyle Kelley and David Harris

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Very High Radix

• Previous designs are Radix-2
• 1 bit of x per PE
• Higher radix designs reduce latency
• Process more bits of x per PE
• Require integer multiplication instead of AND
  gates

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Montgomerys Algorithm

• Multiply Z X Y
• Reduce reduce Z M mod R
• Z Z reduce M / R
• Normalize if Z M then Z Z M
• M satisfies RR-1 MM 0
• Drives LSBs to 0

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Scalable Very High Radix Algorithm

• w-bit words of M and Y e n/w
• v-bit digits of X f n/v radix 2v
• Z 0
• for i 0 to f-1
• (CA, Zw-10) Zw-10 X(i1)v-1iv Yw-10
• reduce (M'v-10 Zw-10)v-10
• (CB, Zw-10) Zw-10 reduce Mw-10
• for j 1 to e1
• (CA, Z(j1)w-1jw) Z(j1)w-1jw
  X(i1)v-1iv Y(j1)w-1jw CA
• (CB, Z(j1)w-1jw) Z(j1)w-1jw
  reduce M(j1)w-1jw CB
• Zjw-1(j-1)w (Zjwv-1jw,
  Zjw-1(j-1)wv)

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Very High Radix PE
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Very High Radix Pipeline Timing
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Latency

• Tenca-Koç k n/p
• Very High Radix k n/pv

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Implementation

• C and Verilog reference models
• Parameterized by w, p, and v
• Extensive testing up to n 1024
• Synthesized Verilog onto FPGA
• Xilinx Virtex II Pro XC2V2000-6

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Results
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Further Work

• Use of rectangular w x v-bit multipliers
• ASIC implementation
• Parallelization techniques
• Quotient pipelining (redundant form)