Design Verification of Athena

1
Design Verification of Athena

• presented by
• Laura Harris
• Faye Kasemset
• Jacob Stultz
• Amy Wibowo

2
Motivation

• The Problem Too Much Heat. When Moores Law no
  longer holds true, how will we keep increasing
  the speed of applications?
• Our Solution Reconfigurable Application Specific
  Computing (RASC). ASICs provide higher-speed
  computing for specific needs, but time-consuming
  and expensive. Instead, we use FPGAs.

3
What is Athena?

• Board that connects FPGA to host system

NumaLink
NumaLink
4
FPGA Core Services

• SSP port communication with system
• SRAM read and write ports
• Algorithm control
• Control and status registers
• Host and FPGA synchronization
• Global clock generation and control

5
FPGA diagram

SSP
SRAM Interface
MMRs
DMA WR
Alg Block
DMA RD
PIO
Alg Control
6
Testing in Simulation

• FPGAs are reprogrammable much easier to fix than
  ASICs.
• BUT, wiring up signals to an analyzer is a pain.
• Simulation lets us see ANY signal we want.

7
Algorithm Design

• Empty module with outputs and inputs that
  interface with system
• Read from SRAM, compute, write to SRAM
• Must request permission to Read/Write to SRAM
• 4 speeds 200, 100, 66, and 50 MHz

8
Design ? Bitstream

• Synthesis verilog ? logical primitives ? FPGA
  primitives (FPGA specific)
• Build combines many netlists into 1 file
• Map FPGA primitives ? built-in higher level
  blocks
• Place and Route decides location of all elements
  on FPGA, and paths between elements. Tries many
  configurations to find best.
• Timing Analyzer checks timing requirements
• Bitstream loaded onto FPGA chip

9
Algorithm Suite

• presented by
• Amy Wibowo

10
Algorithms needed

• Algorithms that let us test
• Max number of logic levels between 2 flops
• Max usage of FPGA
• Can we use all debug registers?
• What is best for guided placement?

11
Logic Levels Algorithm
M blocks

• M controls FPGA utilization
• N logic levels between flops
• Tried for all possible memory configurations
  (i.e. read from sram 0 and 1 and write to 1 and
  0, etc.)

N inverters
12
Debug Algorithm

• connects 64 debug registers
• Addresses
• Results
• Intermediate results
• Both combinational and registered data
• Results
• Could only connect 20 debug registers
• Restructured debug mux so now all 64 debug
  registers place and route

13
Golden Placement

• Utilizes all of core services
• Uses all 64 debug registers
• Includes a complex stepping module
• .ncd file (from map and place and route) is used
  as a starting point for placing other designs
• Does it speed up and/or improve PAR?

14
Outcome

• Practical skills Verilog, Unix familiarity,
  Xilinx Tools
• Taking an FPGA design from verilog to bitsteam
• Interfacing with an already existing algorithm
  environment
• Set of algorithms that can test future revisions
  of board and compare performance to Athena