Ch' 6: Programmable Logic Devices

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Ch. 6 Programmable Logic Devices

• Types of Programmable Logic Devices (PLDs)
• Programmable Logic Array (PLA)
• Programmable AND-Array Logic (PAL)
• Generic Array Logic (GAL)
• PAL, Configurable and Erasable (PALCE)
• Programmable Read-Only Memory (PROM)
• Field Programmable Gate Array (FPGA)

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• Logical Structure of a PLA

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• Transistor-leveldesign for a PLA
• NOR-NOR-invertstructure isequivalent to an
  invert-AND-OR ? Why?

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• Methods for Programming Connections
• Use PLD Programmer (Rom Writer) for Programming
• Determines where connections are to be made

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• Problems with PLAs
• Too many programmable connections
• Mostly unused
• Leads to costly and difficult to manufacture
  devices
• Alternatives to PLAs
• Programmable AND-Array Logic (PAL)
• Fixed matrix of OR gates of various sizes
• Only AND matrix is programmable
• Registerd PAL Device
• PAL with a set of flip-flops that can be
  optionally connected
• GAL, PALCE
• Erasable versions of PALs
• Includes several flip-flops for sequential
  circuit implemention

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• PROMs and EPROMs can also be used as PLDs
• PROM
• Used mainly as a memory device
• Example Boot ROM (BIOS) used in PCs
• EPROM
• Can be erased by exposure to ultraviolet light
• Address lines are connected to inputs (variables)
• Data lines are connected to function outputs
• Programmed connections are the contents of the
  PROM or EPROM -gt minterms

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• LogicalStructureof a PROM

Output of AND gate ?
Output of OR gate ?
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• Example Using a 256 x 4 PROM Device,
• implement f1 wxyxyz xzand f2 aby
  abxy abxy

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Example PAL Structure PAL18L4
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• Example Z0 ABC CD
• Z0 (A B C) (C D) AC BC
  AD BD CD

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Sequential PAL and GAL Devices

• Registered PAL
• Includes registered outputs (outputs of D
  flip-flops)
• GAL and PALCE Devices
• Erasable / reprogrammable versions of registered
  PALs
• Configurable as a combinational or sequential
  device
• Example GAL16V8R
• GAL configured as a PAL16R8 type device
• 8 of the 16 inputs come from the D flip-flop
  outputs
• Question What are these types of inputs called?

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Field Programmable Gate Arrays

• Most complex type of chip that can be
  programmed to implement arbitrary circuits
• Many competing manufacturers
• Actel, Altera, Cypress, Lattice, Xilinx, etc.
• Competitive Factors
• large number of logic gates, high speed,
  flexibility, low cost, reprogrammability (can be
  traded off for speed)
• FPGA
• Definition 1 a programmable array of simpler
  PLDs
• Referred to as a complex PLD (CPLD) by Xilinx
• Definition 2 a field-programmable version of a
  gate array
• Most commonly-used definition

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• Basic Structure ofa Gate Array (asimple ASIC)

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(ab abe)
bcd

• Gate arrayprogrammed toimplementf (ab
  abe) c bcd

(ab abe) c bcd
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• Xilinx Spartan-IIFamily FPGABlock Diagram

Delay-locked loop (DLL)- can be used for clocking
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An LUT is used as auniversal logic device

• One slice of aSpartan-II CLB(two slices total)

Addition is a commonly-usedbase operation in
many types ofsignal processing/computing/otherde
vices a carry-lookahead logicmodule is used
for fast addition.
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• Pinouts forSpartan-IIblock RAMcell

This can be implementedas a single-port or
dual-port RAM the use of a dual-portRAM enables
concurrentreads and writes as long asthe
read/write addresses aredifferent.
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FPGA Configuration Methods

• Use special FPGA programmer devices
• similar to a PLD programmer (ROM writer)
• with SRAM-based configuration, data is lost once
  the FPGA is extracted from the FPGA programmer
• acceptable method for one-time programmable FPGAs
• Attach PROM to FPGA in application board
• store FPGA configuration in a serial PROM
• FPGA is reconfigured from the PROM when power is
  applied
• Attach EPROM to FPGA in application board
• Custom-designed FPGA programming interface

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FPGA Configuration S/W Support

• Design Entry Tools
• Schematic (drawing-based)
• Language-based (e.g., ABEL, Verilog, VHDL,
  SystemC)
• Logic Simulation Tools
• Functional simulation
• Timing simulation (with back-annotated delay
  info.)
• Outputs
• Simulation output in a timing diagram or table
  format
• Logic Synthesis Tools
• Create logic gate design (netlist) from
  high-level description
• Create configuration file (mapping to available
  gates and wires)
• Also referred to as implementation
• Create appropriate configuration file for target
  FPGA device

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FPGA Programming (Configuration)

• Programming an FPGA from a Configuration File
• Master / slave mode
• master FPGA chip is the initiator and controller
  of the FPGA configuration process
• Serial / parallel mode
• serial configuration data is entered one bit at
  a time
• Synchronous / asynchronous mode
• synchronous data entered in synch with a clock
  signal
• Boundary scan mode
• uses the scan method commonly used for chip
  testing

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Custom-Designed FPGA Prog. H/W

• Helps the user to understand the FPGA structure
  and configuration process (also low-cost
  solution)
• Enables fast FPGA programming and test
• Leads to fast prototyping
• User can experiment with different solutions
  quickly
• Enables reconfigurable computing solutions
• New programming method in which the hardware
  circuit is changed as the software program
  progresses
• Enables the customization of H/W for each S/W
  module

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Spartan XC2S200 Programming

• 3 mode pins used to control programming mode
• Can leave (M0, M1, M2) pins unattached
• These pins have default pull-up resistors
  (default (1,1,1) value)
• Configuration clock pin
• Used to control when config. data is clocked into
  chip
• Make positive transition when data is stable
• Configuration data input pins
• D0 is the serial data input pin
• Many pins have dual uses (for config. or normal
  mode)
• Pins to check config. result (DOUT, PROGRAM, etc.)

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• Configuration circuit for two Spartan-II FPGAs
  connected in tandem

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• Configuration timing waveforms

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• PC-based slaveserial modeconfiguration

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• PC-based boundary scan mode configuration

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• Design for FPGA prototyping board