Lab Environment and Miniproject Assignment

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Lab Environment and Miniproject Assignment

• Spring 2006
• ECE554
• Digital Engineering Laboratory

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Lab Environment

• Ten 2.8 GHz Workstations with 1 GB RAM and 80GB
  Harddrives
• Six 550 MHz Workstations with 512 MB RAM
• Design Tools
• HDL Editor, Core Generator System, FPGA Express,
  Design Manager, Constraints Editor, Modelsim
• Instrumentation
• HP8012 Signal Generator generates system clock
• Hewlett-Packard Oscilloscopes probing logic
  values
• Agilent Logic Analyzers monitor data on output
  pins
• XSV FPGA Boards
• See Lab Environment Handout and FAQ page

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Lab Warnings

• Do not wear static electricity generating
  clothing (wool sweaters)
• Report stuff dripping from ceiling (dont touch
  it).
• Dont sit or stand on backs of chairs or lab
  tables
• Dont probe (with oscilloscope) or touch anything
  on the FPGA board, except for push buttons, DIP
  switches, and special pins for clocks and
  expansion headers
• Do not do any wiring on the board with power on
• Be sure you download the correct files to the
  FPGA
• Carefully read all warnings in Lab Environment
  handout

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XSV FPGA Board
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XSV Board
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XSV Block Diagram
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XSV Board Features

• Xilinx Virtex FPGA (Compute)
• 2 MB Memory (Store for Read/Write)
• Parallel Serial Ports to PC (I/O from/to
  Outside World)
• Keyboard (PS/2) Port
• VGA Output to VGA Monitor
• Audio/Video Converters
• See XSV Board Manual at
• http//courses.engr.wisc.edu/ecow/get/ece/554/kime
  /technicali/

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Current Setup
Parallel Cable
Serial Cable
NT machine running HyperTerminal
Parallel port Configuration download Serial
port Miniproject
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Miniproject Specification

• For the miniproject, you will
• Design a Special Purpose Asynchronous
  Receiver/Transmitter (SPART) and its testbench in
  Verilog/VHDL
• Simulate the design to ensure correct performance
• Download the design and associated files and
  demonstrate correction functionality
• Preparing a report on your design

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Miniproject Objectives

• To get familiar with the lab environment prior to
  the class project and bench exam
• To get practice using HDL in your designs
• To provide the basic I/O interface to the class
  project
• To get experience working with a partner

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SPART Interface
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Processor Interface

• Data is sent/received across the bidirectional
  data bus
• Handshaking (status) signals
• TBR Transmit Buffer Ready (Empty)
• RDA Receive Data Available
• IOCS Chip Select
• IOR/W_ Read or Write Bar signal

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SPART Block Diagram
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Asynch. Serial Communication

• Start bit (1 bit wide)
• Data bits (8 bits)
• Parity(None, Even, Odd) - optional
• Stop bit (1 bit wide)

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Transmitting

• Tx must be tested first.
• Tx shifts the LSB out from Tx buffer first.
• Tx sends stop bit when there is nothing to send.

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Receiving

• Receiver samples the RxD to get the beginning of
  the start bit
• Use resynchronization to avoid metastability
  of any flip-flop

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Baud Rate Generator
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Baudrate and Sampling

• We want the transmission rate to be constant for
  different input clocks
• Baud rates of 4800 and 9600 bit per second
• Sampling rate x16 of the baud rate (bit rate)
• Divide the clock (5 and 20 MHz) to get the
  Enable signal (sampling rate)

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Testbench (Mock Processor)

• A finite state machine
• Receive data on the RxD from keyboard and
  transmit (echos) back on the TxD back to the
  HyperTerminal
• Load Baud Rate Generator with Arbitrary value
• Demonstrate ability to work with different clocks
  and BRG divisor values
• Note that it is not provided.

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Demonstration

• Demos done in lab on 2/6 and 2/7 at start of
  class.

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Report

• Due 2/6 and 2/7
• Verilog/VHDL code for your design with clear
  comments
• Description of the function of the SPART and each
  block in the design, including the testbench
• Record of experiments conducted and how the
  design was tested
• Problems encountered and solutions employed