Berkeley Emulation Engine Hardware Emulation of Communication Systems

1
Berkeley Emulation Engine ?Hardware Emulation of
Communication Systems

• Berkeley Wireless Research Center
• Chen Chang, Kimmo Kuusilinna, Brian Richards,
  Kevin Camera, Nathan Chan, Allen Chan, Robert W.
  Brodersen

2
Whats BEE?

• A real-time FPGA-based hardware emulator, with
  speed up to 60 MHz
• Emulation capacity of 10 Million ASIC
  gate-equivalents per module, corresponding to 600
  Gops (16-bit adds).
• 2400 external parallel I/O providing 192 Gbps raw
  bandwidth.
• Automated design flow from Simulink to FPGA
  emulation, integrated with INSECTA ASIC design
  flow.

3
BEE Applications

• Real-time hardware emulation
• Novel Communication Systems with analog front-end
  hardware (MCMA, UWB, 60GHz)
• Digital signal processing systems
• Real-time control systems
• Neuron-like network processing
• Hardware acceleration
• Large communication/signal processing system
  simulation
• Hardware-in-the-loop cosimulation with software
  system
• Complex parallel computing algorithms

4
The BEE Design Environment
Analog Front-end
Servers
BEE Processing Unit
Client PC
Network
Ethernet
LVDS/LVTTL
BEE/Insecta Design Flow
FPGA Bit Stream Conf File
Simulink MDL
ASIC Layout
5
BEE System Assembly
20 Virtex-E 2000 16 ZBT-SRAM (1MByte each) 8
Riser I/O Cards
Riser I/O Card
MPB
StrongARM Module Linux OS
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Hardware Performance

• Board-level Main Clock Rate 160MHz
• On Board connection speed
• FPGA to FPGA 100MHz
• XBAR to XBAR 70MHz
• Off board connection speed (3 ft SCSI cable loop
  back through riser card)
• LVTTL 40MHz
• LVDS 160MHz 220MHz

7
Hardware Capacity

• Reference Design
• 10240 tap FIR filter
• 512 taps per FPGA
• Slice utilization 99 of 19200 slices
• Max Clock Rate 28.5MHz
• ASIC Gate 401K per FPGA, 8M total
• MOPS 583,680 total (16bit add 12bit cmult)
• Power 2.5W per FPGA, 50W total

8
Run-time Data I/O Interface
Matlab Control GUI

• New and improved infra-structure for transferring
  data to and from the BEE
• Control all data transfers from within a local
  Matlab GUI
• Accepts standard Simulink data structures for
  intrinsic reuse of existing test vectors
• Library macro contains the entire hardware
  interface in one fully parameterized block

Ethernet
BEE
Linux/StrongARMDaemon
EmbeddedController
RAM
RAM
User Design
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Data I/O Interface Hardware
Pin Gateways
Source RAM
Bus Protocol Controller
Sink RAM
10
Data I/O Interface Software

• Specify input source, BEE hostname, and data bus
  parameters in Matlab GUI
• Utilizes a custom MEX socket library for network
  connectivity
• Uses a simple packet header to distinguish
  control frames and byte streams

root ./daemon Listening on port 2108
okWaiting for connection...

• StrongARM (running embedded Linux) starts a
  persistent, lightweight server
• Matlab clients connect via TCP and either send a
  data stream or read request
• Incoming data is translated into the hardware
  protocol and broadcast to FPGA

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BCJR MAP Decoder

• E2PR4 Channel Encoder - Decoder
• Fully enclosed design
• Uniform RNG input vector
• Channel encoder
• AWGN filter
• Channel decoder
• BER collection mechanism
• Part of Full 3G Turbo Decoder

12
BCJR As Case Study

• 10 MHz system clock
• SNR 14db ? -1db
• 109 Samples

13
Conclusion

• 4 BEE units are in service
• 6 Win2K servers are available for design flow
  usage
• 5 BWRC research groups, 16 students are using
  the current BEE/Insecta flow

14
Main Processing Board
48 bit buses
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Processing Board PCB

• Board Dimension 53 X 58 cm
• Layout Area 427 sq. in.
• No. of Layer 26
• Technology 4 Mil Trace
• Manhattan Distance 45,950 in.
• Etch Length 51,804 in.
• No. of Vias 32,334
• Pin Count 28,611
• No. of Nets 8,493
• No. of Connections 19,877
• Total Components 3,400
• Bypass Capacitors 2,40

16
Off Module Riser I/O Cards
68 Pin HD SCSI Connectors 48 signals per
connector
Source (Xilinx only)
Destination
LVDS Termination Resistor Arrays
400 pin VHDM-HSD Right Angle PCB Connector
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Controller Module

• 206MHz StrongARM 1110 Processor
• 32MB SDRAM
• 16MB Flash ROM
• 10Base-T Ethernet with RJ45 jack
• Compact Flash slot for expandability
• Linux Kernel 2.4 as OS
• Remote FPGA configuration and read-back through
  GPIO

18
Power Distribution System

• Max Input Power 800Watt
• Max Processing Power 600Watt
• Max Current 600A

19
Power Board

• 6 Layer PCB
• 25 Mil Trace
• 10 DC-DC converters (max 60A output current each)
• 25 Terminal Blocks (max 60A current per circuit)