MC9S12DP256 Block Diagram

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MC9S12DP256 Block Diagram
256k byte Flash 12k byte RAM 4k byte EEPROM
2.5v Voltage Regulator (5V Source)
16-bit CPU12 With Background Debug Interface
PLL Clock Generator
CPU12 Enhancements 1- New math instruction
Addressing modes 2- Extended multiply and
divide 3- Table look-up and interpolate 4- Fuzzy
logic instructions 5- 50Mhz CPU clock speed 6-
Voltage regulator 7- 2.5V operation See next
page
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HC11 to HC12
Accumulators Index Register X Index Register
Y Stack Pointer Program Counter Condition Code
Register
Inherent Immediate Direct Extended Relative Bit
Manipulation Indexed
Inherent Immediate Direct Extended Relative Bit
Manipulation Indexed
Indexed with Post/Pre Increment Indexed with
Post/Pre Decrement Indexed with Accumulator
Offset Indexed Indirect Indexed Indirect with
Accumulator Offset
Enhancements Added new addressing modes allowing
unlimited number of memory pointers that can be
used to point for jump and branch tables. These
addressing modes provide efficient C language
usage.
Source Code Upward Compatible
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MC9S12DP256 Memory Map
Linear Addressing is easier for Assembly Language
Programming But it Makes Most Instructions Longer
and Slower in a 16-bit Architecture To Allow the
Larger Addresses to be Specified in Instructions
Bank Switching Lowers System Cost with Smaller,
Faster Instructions But it Requires Consideration
for Interrupt Management To Assure Efficient
Software Control
NOTE Values shown are for 9S12DP256. All PPAGE
values begin with 3F and work down (e.g. DP256
3F?30 DP512 3F?20).
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MCS12 Bank Switching
JSR Jump to Subroutine
RTS Return from Subroutine
PCHPCL M(SP)M(SP1)
SP SP - 0002
M(SP)M(SP1) RTNHRTNL
SP SP 0002
PC Subroutine Address
4 Bus Cycles
5 Bus Cycles
JSR Label
RTS
CALL Call Subroutine in Expanded Memory
RTC Return from Call
SP SP - 0002
PPAGE M(SP)
M(SP)M(SP1) RTNHRTNL
SP SP 0001
SP SP - 0001
PCHPCL M(SP)M(SP1)
M(SP) PPAGE
SP SP 0002
PPAGE Page
PC Subroutine Address
CALL Label,Page
RTC
7 Bus Cycles
7 Bus Cycles
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MC9S12DP256 Flash Memory Features

• 256k bytes of Flash made up of four 64k byte
  blocks
• Reads as byte or word
• Programming is by aligned word (2 bytes on 2 byte
  boundary)
• Support for fast burst programming (32 word
  row)
• All four Flash blocks can be programmed and
  erased in parallel
• Sector Erase is by 256 word sector (512 bytes on
  0.5 Kbyte boundary)
• Automated program and erase algorithm with simple
  command sequence
• Flexible protection scheme against accidental
  program or erase
• Can read/execute from one array while writing
  another
• Optional interrupt on command completion and
  command buffer empty
• Pre-scaler register allows application to tailor
  the state machine clock
• Single supply for program and erase

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MC9S12DP256 Flash Memory Features

• High Speed Programming (FCLK 200kHz derived
  from input clock)
• Flash Word Program in 46 µs
• Flash Burst Program of 32 Words in lt21 µs / word
• Flash 512 Byte Sector Erase in 20 ms (256 word)
• Flash 64k Mass Erase in 100 ms (blocks can be
  erased in parallel ? 256K 100 ms)

• Further Reading
• AN2204/D Fast NVM Programming for the
  MC9S12DP256
• AN2206/D Security and Protection on the
  MC9S12 Family
• AN2213/D Using Cosmic Softwares M68HC12
  Compiler for the MC9S12DP256
• AN2216/D MC9S12DP256 Software Development
  using Metrowerks CodeWarrior
• AN2153/D A Serial Bootloader for
  Reprogramming the MC9S12DP256 Flash Memory

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HCS12 Background Debug Mode (BDM)
Non-Intrusive Debug of Application Software
Hardware Back Door into the CPU
Single-wire communication with host development
system
Active out of reset in special single-chip mode
Nine hardware commands using free cycles, if
available, for minimal CPU intervention
Instruction tagging capability
Software control of BDM operation during wait mode
Software selectable clocks
Remember Always boot into single chip mode
even if using external memory.
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HCS12 Clock Reset Generator (CRG)

• gtCrystal Oscillator
• gtPhase Locked Loop
• gtSystem Clock Generator
• gtSystem Reset Generator
• gtReal-Time Interrupt
• gt25 MHz max Bus Speed
• gtClock Quality Checker
• gtEnhanced Check using VCO PLL and System
  Operation
• gtClock Monitor
• gtCourse Check via RC Time Delay

Bi-directional Reset Pin
Colpitts Oscillator Configuration
Always install for maximum flexibility using PLL
Enhanced RTI Flexibility Can Operate in Pseudo
Stop Mode
Enhanced PLL Control
The feature allows the CPU to shut Down the
entire MCU but leaving The RTI circuit running
so that the CPU can keep track time of
day Accurately.
Self Clock Mode Operates at PLLs Natural
Frequency (2 5 MHz) And Does Not Require Any
External Components
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HCS12 Port Integration Module (PIM)
Each port in PIM module has a data
direction Register, a data register, pin output
status Register, pull-up/pull-down and reduced
drive capability. ----------------------
--------------------------------------------------
--- Port A, Port B, Port E are not part of the
PIM Module and do not have pin output status.
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HCS12 I/O Pin Functionality
Logic Thresholds High 0.65 x VDD Low 0.35 x
VDD
Output Drive Currents Output High Full
Drive 10mA _at_ VDD 0.8v Partial Drive 2mA _at_
VDD 0.8v Output Low Full Drive 10mA _at_ 0.8v
. Partial Drive 2mA _at_ 0.8v .
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HCS12 Microcontroller Technology Leadership

• True 16-bit Architecture
• 16-bit Data Bus and 2-byte Instruction Queue
• Efficient 8-bit Op Codes
• Instructions are between 1 to 6 bytes in length
• Efficient Bank Switched Memory Scheme
• PLL Clocking
• Industry Best 0.25µ Flash
• EMC/EMI Performance Focus
• Tested against SAE Noise Emission Specification