Lectures Wed 10'15 12, room TB220

1
TKT-1510 TestattavuussuunnitteluTKT-1516 Design
for Testability

• Lectures Wed 10.15 12, room TB220
• Instructor Olli Vainio
• 3 credits
• Prerequisites (recommended)
• TKT-1212 Implementation of Digital Systems
• - Basic knowledge of digital circuits, Boolean
  algebra and integrated circuits
• Requirements Final exam

2
Exercises

• Homework assignments are given, to be discussed
  in class.
• Homework is voluntary, but there is a bonus
  system with the homework exercises. Returned
  written solutions will be give 0.5 bonus points
  for the exam.

3
Literature

• Fault Tolerant Fault Testable Hardware Design ,
  by P.K. Lala, pp. 1 - 66
• Design for Test for Digital ICs and Embedded
  Core Systems, by A.L. Crouch
• Application-Specific Integrated Circuits, by M.
  J. Smith (available in the Internet), chapter 14
  (supplementary)
• CMOS VLSI Design, by Weste and Harris, chapter 9
  (supplementary)

4
Course Objective

• To learn basics of testing and design for
  testability for digital circuits and
  systems-on-chip.

5
Course Contents

• Basic concepts of reliability
• Fault models in digital circuits
• Fault detection 
• Automatic test pattern generation
• Scan architectures and techniques
• Memory test architectures and techniques
• Testing embedded cores

6
Motivation

• Testability is an important quality metric in
  electronic systems
• Cost of test is beginning to dominate the
  per-part cost of mant silicon products, e.g., in
  consumer market
• Time-to-market pressures force the need of
  structured, repeatable and automatic test
  features as part of overall design methodology
• In system-on-chip designs, test data management
  and cost of test are important
• Reusable IP blocks need designed-in test features
• Learn terminology
• Industrail demand, employment opportunities

7
Testing and Diagnosis

• Testing the system is exercised and the response
  is analyzed to check whether it behaved correctly
• Diagnosis if incorrect behavior is detected,
  locate the cause of misbehavior.
• - Assumes knowledge of the internal structure
  of the system

8
Main Categories of Tests

• Logic verification or functionality tests
• - Done before chip tapeout to verify the
  functionality of the design
• Silicon debug
• - Run on the first batch of chips that return
  from fabrication
• - Confirm that the chip operates as intended
  and help debug any discrepancies
• - Can be done at full speed, more extensive
  than logic verification tests
• - Less visibility inside the chip compared to
  design phase

9
Main Categories of Tests

• Manufacturing test or Production test
• - Done on each manufactured chip before
  shipping to the customer to verify that the
  silicon is completely intact
• - Verify that every transistor, gate, and
  storage element in the chip functions correctly

10
Yield

• Not all die on a wafer function correctly
• There may be bridged connections or missing
  features due to dust particles, imperfections in
  materials or photomasking, etc.
• Imperfections may result in a fault
• Yield is the number of good die divided by the
  total number of die per wafer
• The goal of a manufacturing test procedure is to
  determine which die are good and should be
  shipped to customers

11
Cost of Detecting a Fault

• Wafer 0.01 - 0.1
• Packaged chip 0.1 - 1
• Board 1 - 10
• System 10 - 100
• Field 100 - 1000

12
Exhaustive testing
n
Combinational logic
13
clk
reg
m
m
Combinational logic
n
Example n 25 m 50 Test takes 1 ms per pattern
14
Basic Digital Debugging

• When a chip returns from fabrication, the first
  tests are run in a lab environment
• Need a circuit board with features to support
  testing
• - Power for the IC with ability to vary VDD and
  measure power dissipation
• - Analog and digital inputs and outputs as
  required
• - Clock inputs as required
• - A digital interface to a PC
• - Zero insertion force socket for the chip

15

• The chip should have a serial UART port or some
  other interface that can be used independently of
  the normal operation of the chip
• Software should provide for peeking (reading) and
  poking (writing) registers in the chip
• Also an interface for a logic analyzer may be
  provided

16
Initial Steps in Chip Testing

• Smoke test ramp up supply voltages from zero
  without clocks running and monitor the current.
• Enable the clocks, some dynamic current should be
  evident. If possible, initially use reduced clock
  speed.
• Examine various registers using PC-based peek and
  poke software, checks the integrity of the
  interface.
• The chip may have built-in self test that can be
  activated over a boundary scan interface.
• Otherwise, the functionality is checked from the
  bottom-up.
• Top-level test like running a piece of code at
  once often does not work, usually because of
  problems with the test fixture.

17
Some Pointers for Debugging

• Keep a dated logbook for all tests done.
• Do one change at a time and observe the result.
  Changing many things will not logically lead to
  the bug (shotgun approach).
• Check everything two or three times never assume
  anything unless it is measured and logged in a
  notebook.
• Check signals and supply voltages at the pins of
  the IC new test boards may have errors.
• Perform continuity checks from the IC pins to
  expected places
• Never count out a possible reason for a bug

18

• Use freeze spray or heat gun to check for
  temperature problems.
• Check the state of any internal registers
  against documentation.
• Evaluate the timing of inputs and outputs with
  respect to the clock. Setup or hold times may be
  violated in a new test setup.
• When a bug is discovered, hunt for other portions
  of the design that might have a similar bug.
• Never assume anything question everything.
• When the chip is demonstrated to be operational,
  you can measure more subtle characteristics such
  as performance.

19
Testers and Test Fixtures

• A tester is a device that can apply a sequence of
  stimuli to a chip or system under test and
  monitor and/or record the results
• Four general types of test fixtures are
• - A probe card to test wafers or unpackaged dies
• - A load board to test a packaged part
• - A PCB for bench-level testing (with or without
  tester)
• - A PCB with the chip in situ, demonstrating the
  application for which the chip is used

20
Handlers

• An IC handler feeds ICs to a test fixture
  attached to a tester.
• Devices are gravity-fed to a handler, which
  mechanically picks the chips up and places them
  in the test socket on the load board.
• The tester stimulus is then applied and chips are
  binned depending on whether or not they passed
  the test.

21
Shmooing

• The ability to vary the voltage and timing on a
  per-pin basis with a tester allows a process
  called Shmooing.
• For instance, vary VDD from 3 V to 6 V while
  varying the tester cycle time.
• A shmoo plot shows the sensitivity of the part
  with respect to voltage.
• Another example of shmoo is to skew the timing on
  inputs with respect to clock to look for setup
  and hold variations.

22
Shmoo plot

• 1.0
• 1.1
• 1.2
• 1.3
• 1.4
• 1.5
• 1.0 1.1 1.2 1.3 1.4 1.5
• voltage
• Normal, well-behaved shmoo
• Typical speedpath

Clock Period in ns
indicates failure
23
Shmoo plot

• 1.0
• 1.1
• 1.2
• 1.3
• 1.4
• 1.5
• 1.0 1.1 1.2 1.3 1.4 1.5
• voltage
• Brick wall
• Bistable initialization

Clock Period in ns
24
Shmoo plot

• 1.0
• 1.1
• 1.2
• 1.3
• 1.4
• 1.5
• 1.0 1.1 1.2 1.3 1.4 1.5
• voltage
• Wall
• Fails at a certain voltage (coupling, charge
  sharing, races)

Clock Period in ns
25
Shmoo plot

• 1.0
• 1.1
• 1.2
• 1.3
• 1.4
• 1.5
• 1.0 1.1 1.2 1.3 1.4 1.5
• voltage
• Reverse speedpath
• Leakage

Clock Period in ns
26
Shmoo plot

• 1.0
• 1.1
• 1.2
• 1.3
• 1.4
• 1.5
• 1.0 1.1 1.2 1.3 1.4 1.5
• voltage
• Floor
• Works at high but not low frequency (leakage)

Clock Period in ns
27
Shmoo plot

• 1.0
• 1.1
• 1.2
• 1.3
• 1.4
• 1.5
• 1.0 1.1 1.2 1.3 1.4 1.5
• voltage
• Finger
• Coupling

Clock Period in ns