EECEC 320 Introduction To Microprocessors

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EE/CEC 320 Introduction To Microprocessors

• Gary Gear, P.E.
• Professor COE

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Administrative Announcements

• Im going to delay Exam 1
• Probably 2/15

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Serial Communications 1 bit at a time

• We can send data synchronously
• Or not
• Either way we have to know where the bits are
  otherwise they all look the same

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Common RS232 byte frames

• BAUD rate refers to the bit time rate data is
  being transferred
• 9600 BAUD means 9600 bit times per second
• Standard RS 232 Baud rates are
• 9600
• 4800
• 2400
• 1200
• 300
• 120 (very slow)

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It takes more bit times than bits to create a
serial byte frame

• Typically there is 1 start but and 1 or 2 stop
  bits
• There can be 7 or 8 data bits
• Frequently if you use 7 data bits (ASCII data)
  the 8th bit space is designated parity bit
• Refer to the diagram Im about to draw on the
  board (this shows 10 bit times per byte of data
  the most common case)

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Each bit time is divided into 16 clock states

• Usually a UART will have a prescale register so
  that what ever crystal you chose will produce 16
  clock states at your chosen Baud rate.
• Only certain specific crystal frequencies will
  produce exactly 16 clock states at any common
  Baud rate
• Thats why we use the 11.0592 MHz and 22.118 MHz
  crystals for the 8051

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Matching UARTS

• The transmitting UART and the Receiving UART must
  be configured to produce the same clock state
  frequency (almost) in order to communicate
• Almost means there is an allowable error in
  frequency match
• The error window
• I could talk for days on this -)

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The communication implementation means

• RS 232 communications is a protocol - a specific
  method of framing bytes into recognizable
  sequence of state transitions
• RS 232 protocol can be implemented in
• Wire
• Fiber
• Infrared
• Only voltage specifications for wire
  communications are specified in the formal RS 232
  specification
• -12V to 12 V
• Most PCs today will also accept 0 to 5 volt RS
  232 input (ours do)
• All communications implementations are flawed.
  They produce some measurable error rate

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How errors can be detected

• Bit time framing
• Parity Bits
• Encapsulating your data into packets with error
  detection and/or correction
• More on this later

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How the Transmitter and Receiver synchronize

• The 16 clock state generators must closely match
• The leading edge of the start bit from the
  Transmitter starts clock state counting in the
  Receiver
• From that point forward (10 or 11 bit times), the
  transmitter and Receiver must not differ by more
  than 1 or 2 clock state counts

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Refer to the 8250A/16550D Data Sheet

• The 8250 has become (more or less) the UART
  architecture for RS 232 serial communications
• The PC uses the 8250 UART architecture for COM
  ports
• Over the years, there have been variations that
  all maintain register compatibility with the 8250
• I designed Intels first version of the 8250A
  UART chip but I cant remember much about it -
  brain overflow error _at_-(

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RS 232 byte framing

• The 8250 is fully compliant with all of the RS
  232 standard byte frames
• Registers are used to tell the 8250 what framing
  mode to use

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Highlights (Features section)

• Internal divide counter that creates a (Baud rate
  16) internal clock
• Transmit state machine and receive state machine
  are completely separate - they only share the
  internal (Baud16) clock
• There are holding shift registers
• False start bit detection
• framing error detection
• Hardware hand shake
• Standard Microprocessor interface

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Input Buffering

• The receive state machine has an output holding
  register
• As soon as an incoming byte is received, the data
  byte is transferred to the holding register so
  that the next data byte can be clocked in
• The microprocessor has until the second byte is
  clocked in to read the first byte and clear the
  holding register
• If the microprocessor fails to read the holding
  register in time - an overrun error is generated
• Buffered UARTS (Newer variation of the 8250) has
  a queue of holding registers (give the micro more
  time to service the UART)

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Output Buffering

• The Transmit State Machine has an output holding
  register
• By keeping the output holding register serviced,
  maximum byte transfer rate can be maintained

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Hand Shake

• What if the receiving UART is full?
• Hardware handshake allows the receiving UART to
  pause or delay transmission of data bytes
• This is useful if the microprocessor is busy
• Two means of hardware handshake are available on
  the 8250

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The 8051 Implementation

• In Modes 1 and 3, Timer 1 is used as the Baud
  Rate Generator
• If you use the serial port, you sacrifice one
  timer
• Serial Control is with SCON
• There is no hardware hand shaking built in to the
  UART
• You must consider microprocessor timing
• 9th bit interrupt mode for interprocessor
  communications

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SCON
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Serial Modes

• Mode 0 Shift Register
• Fixed Baud rate at OSC/12
• Mode 1 8 bit UART Most Common
• Baud Rate set by Timer
• Mode 2 9 bit UART
• Fixed at OSC/64 or 32
• Mode 3 9 bit UART
• Baud Rate Set By Timer
• We will be using Mode 1
• Compatible with PCs
• SCON 0x50

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Common Baud Rates

• We will use 9600 Baud with a crystal oscillator
  frequency of 22.118 MHz T1 reload value 0xfa

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Set-up Parameters

• / Set-up interrupts /
• EA 0
• /Set Timer Registers /
• TMOD 0x20
• SCON 0x50 // serial 8 data bits 1 stop bit
• TL1 0xFa // 9600 at 22.118
• TH1 0xFa
• TR1 1 // turn timer 1 on
• ES 1
• EA 1

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Serial Connectors
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Null Modem Connection

• 25 pin serial connector

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Demo