THE MICROPROCESSOR INTERFACE

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THE MICROPROCESSOR INTERFACE
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Memory-Mapped Input / Output

• Existing address, data, and control buses handle
  I/O transactions as if they were normal memory
  accesses
• Disadvantages
• Data transfers must be of the same width as a
  normal memory access
• processors address space must be dedicated to
  I/O space
• Lack of special-purpose I/O signals

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Essential Components of a Memory-Mapped I/O
I/O port Interface between the CPU and the
peripheral hardware
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Direct Memory Access (DMA)

• bypass the CPU-peripheral bottleneck
• transfer data between peripheral and RAM without
  CPU intervention
• allows exceedingly high data transfer rates
• Direct Memory Access Controller (DMAC)
• single LSI chip
• able to take control of the system bus

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Hardware Needed to Support DMA mode I/O
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Direct Memory Access Controller (DMAC)

• DMACs are connected to the processors address,
  data, and control buses exactly like any other
  peripheral
• The CPU can read from and write to the DMACs
  internal registers
• A minimum DMAC register set includes
• address register - points to the
  source/destination of data to be transferred
  from/to memory
• A count register that contains the number of
  bytes to transfer
• Status and Control registers

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DMA Operation

• The CPU sets up a DMA operation by writing the
  appropriate parameters into the DMACs registers
• The DMAC then requests access to the system bus
• When granted access by the CPU, the DMAC opens
  bus_switch1 and closes bus_switch2 and
  bus_switch3 (Fig. 8.14)
• The DMAC puts out an address on the address bus,
  and generates all the control signals necessary
  to move data between the peripheral and memory
• Two control signals, busy and done, synchronize
  data transfers between the DMAC and an external
  peripheral
• When all the data has been transferred, the DMAC
  may interrupt the CPU, if it is so programmed

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DMAC modes

• DMACs and CPUs are designed to work together
• DMAC must be able to both
• Emulate CPU bus cycles
• Request the bus from the CPU
• DMACs either
• interleave DMA operations with normal CPU memory
  accesses
• or
• operate in a burst mode, carrying out a number of
  DMA cycles at a time

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Block Diagram of 68430 DMAC
address data lines muxed
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Interfacing the 68430 DMAC to 68000 System

• OWN
• active-low open-collector output
• activated when DMAC is bus master
• DBEN (Data Bus ENable)
• active low open-collector output
• asserted when DMA is being accessed by CPU

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Block Diagram of 68430 DMAC Interface
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The 68430 DMAC Peripheral Interface

• REQ (request)
• Asserted by peripheral to requests service
• causes DMAC to request control of the bus from
  the current bus master (i.e. the 68000 CPU)
• ACK (request acknowledge)
• asserted by DMAC to indicate that it has control
  of the bus and cycle is now beginning
• RDY (device ready)
• asserted by peripheral to indicate to the DMAC
  that valid data has been stored or put on the bus
• DTC (device transfer complete)
• asserted by the DMAC to indicate to the
  peripheral that the requested data transfer is
  complete
• DONE (done)
• dual-function, active-low input or output pin.

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(No Transcript)
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Table of the 68430 DMACs Registers
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The DMA Operation

• A DMA operation is set up by loading the memory
  address counter (MAC) with the location of the
  source/destination of the 1st operand
• The MAC automatically increments after each data
  transfer
• The increment is 1, 2, or 4, depending on whether
  the DMAC is programmed to transfer bytes, words,
  or longwords, respectively
• The 16-bit memory transfer counter (MTC) is
  initialized by loading it with the number of
  transfers to be made during the current operation
• The MTC, is decremented after each transfer
• The interrupt vector register (IVR) is loaded
  with the vector to be placed on the data bus when
  an IACK cycle initiated by the CPU
• Resetting the DMAC presets the IVR to 0F, which
  corresponds to the un-initialized vector exception

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Operating Mode and Control Registers

• The operating mode of the 68430 is determined by
  
• DCR - Device Control Register
• OCR - Operation Control Register
• CCR - Channel Control Register
• DCR Bit 15 determines if DMAC operates
• in burst mode (DCR15 0),
• in cycle steal mode (DCR15 1)
• OCR bits 7, 5 and 4 determine direction size of
  data transfer
• OCR7 1 ? data transferred from peripheral to
  memory
• OCR5 and OCR4 determine the size of each operand

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Bits OCR4 and OCR5
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Operating Mode and Control Registers (Contd)

• CCR bits 7, 4, and 3
• When CCR7 makes a 0 ? 1 transition (under
  software control), the DMA operation is initiated
• Bit CCR4 is a software abort
• may be set to terminate the current data transfer
  and to place the DMAC in its idle state
• Bit CCR3 is an interrupt enable bit
• The Channel Status Register (CSR), together with
  the Channel Error Register (CER), indicates the
  status of the DMAC to the host CPU