CPE 431531 Chapter 2 Instructions: Language of the Computer

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CPE 431/531Chapter 2 Instructions Language
of the Computer
Swathi T. Gurumani Modified From Slides of Dr.
Rhonda Kay Gaede UAH
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Information

• There is no subi instruction
• Use addi with constant -12
• Hw2 assigned (webpage)
• Due next Thursday (09/14/06)

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2.9 MIPS Addressing for 32-Bit Immediates and
Addresses Addresses

• Addresses in Branches and Jumps
• j 10000
• bne s0, s1, Exit
• PC Branch address ? PC relative addressing
• Elaboration For jumps, we give only 28 bits,
  from whence springeth the other 4? (PC)
• Branching Far Away
• Inserts an unconditional jump to branch target
  and inverts the condition of branch

beq s0,s1, L1 ? bne s0,s1, L2 j
L1 L2
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2.9 MIPS Addressing Addressing Mode Summary

• MIPS Addressing Mode Summary
• Register
• Base
• Immediate
• PC-Relative
• Pseudodirect

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2.10 Translating and Starting a Program
Pseudo Instructions Move
Loader A systems program that places an object
program in main memory so that it is ready to
execute

• Linker
• Place code and data modules in memory
• Determine address of data and instruction
  labels
• Patch both internal and external references

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2.11 How Compilers Optimize

• High-level Optimizations
• Procedure inlining
• Loop Unrolling
• Local and Global Optimizations
• Common Sub expression elimination
• Strength Reduction
• Constant/Copy Propagation
• Dead store elimination

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2.16 Real Stuff IA-32 Instructions The Early
Years

• 1978 8086 16-bit architecture
• 1980 8087 floating point coprocessor, extends
  8086 with 60 floating point instructions
• 1982 80286 extended 8086 architecture address
  space to 24 bits
• 1985 80386 extended 80286 to 32 bits, new
  addressing modes and operations, GPR machine
• 1989-1995
• 1989 80486, 1992 Pentium, 1995 Pentium Pro
• Aimed at higher performance, instruction to help
  multiprocessing
• 1997 MMX floating point stack to accelerate
  multimedia

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2.16 Real Stuff IA-32 Instructions The Later
Years

• 1999 Pentium III 70 SSE instructions, SP FP
  data type
• 2001 Pentium 4 -144 SSE2 instructions, double
  precision arithmetic operations, pairs of 64 bit
  FP operations in parallel
• 2003 AMD extensions to increase address space
  from 32 to 64 bits, long mode for 64 bit address
  data
• 2004 EM64T Intels 64-bit version, SSE3 for
  video encoding and complex arithmetic, graphic
  operations
• This checkered ancestry has led to an
  architecture that is difficult to explain and
  impossible to love. What it lacks in artistry, it
  makes up in volume.

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2.17 Fallacies and Pitfalls

• Fallacy More powerful instructions mean higher
  performance.
• Fallacy Write in assembly language to obtain the
  highest performance.
• Pitfall Forgetting that sequential word
  addresses in machines with byte addressing do not
  differ by one.

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2.18 Concluding Remarks

• Four design principles
• Compiler and optimizations
• MIPS instruction set Fig 2.47
• Instruction Occurrence Fig 2.48